No.11S098-03
29
STC-GE33OX/GEC33OX
Users guide Rev. 1.03
3.4 Development guideline
3.4.1 Module and constraints files
3.4.1.1 Top file
Top file is Power_plus.001.v file. Assign own codes onto this file.
3.4.1.2 Pin assignment and the timing constraints file
Pin assignment and the timing constraints file is power_plus.000.ucf file.
Add all constraints of own design onto this constraints file.
3.4.1.3 Structure of the sample code
3.4.2 Important design cautions
As you design the program in the user FPGA, it is essential to synchronize all processes to the clock pulse
rising edges given from the FPGA's pin number F11 (symbol CLKIN). Follow the four important notices listed
below along with the (Fig-8) Conceptual drawing of the FPGA programming.
Caution
1) Latch all signal timings of the image data, LVAL and FVAL coming from Sentech FPGA at the rising edges
of the clock pulse (symbol CLKIN).
2) In the same manner, the signal timings of the image data, LVAL and FVAL after image processing must be
latched at the rising edges of the clock pulse (symbol CLKIN).
3) When a selector is used in the process as shown as an example in the drawing, the signal timings of the
image data, LVAL and FVAL must be latched at the rising edges of the clock pulse (symbol CLKIN).
4) The image data, LVAL and FVAL must be latched at the rising edges of the clock pulse (symbol CLKIN)
before sending them back to Sentech FPGA.
dis_erea_number_top
(Verilog)
mig_dcm_ddr2
(Xilinx IP Core)
mig_ddr2_wrapper
(ngc)
frame_memory_cnt
(ngc)
bin_caluc_gc
(Verilog)
img_sig_delay_2c
(Verilog)
div_capture_bin
(Verilog)
gc_dis_number_top
(Verilog)
edge_detect_top
(ngc)
img_sig_delay_1line_7c
(Verilog)
div_capture
(Verilog)
uart_top
(ngc)
cnt_device_dna
(Verilog)
dis_device_dna
(Verilog)
DNA_PORT_inst
(Xilinx Library)
Top module
power_plus_001
(Veriolog)
Control Frame Memory
for DDR2 Function
Binarize &
Calculate
center of gravity
Function
Detect Edge
Function
Read Device DNA
Function
Recive UART
Function
Fig. 7 Structure of the sample code
