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SM-B69

SM-B69 User Manual - Rev. First Edition: 1.0 - Last Edition: 1.1 - Author:A.R - Reviewed by M.B. - Copyright © 2020 SECO S.p.A.

42

US/ USB3_SSRX-: USB 3.0 Port #5 Superspeed Receive differential pair.
For EMI/ESD protection, common mode chokes on USB data lines, and clamping diodes on USB data and voltage lines, are also needed. Switch with settable
current limit on power lines are recommended.

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Summary of Contents for Smarc SM-B69

Page 1: ...SM B69 SMARC Rel 2 1 compliant module with the Intel Atom X Series Intel Celeron J N Series and Intel Pentium N Series formerly Apollo Lake Processors...

Page 2: ...e best product possible For further information on this module or other SECO products but also to get the required assistance for any and possible issues please contact us using the dedicated web form...

Page 3: ...VIEW 14 2 1 Introduction 15 2 2 Technical Specifications 16 2 3 Electrical Specifications 17 2 3 1 Power Consumption 17 2 3 2 Power Rails meanings 18 2 4 Mechanical Specifications 19 2 5 Supported Ope...

Page 4: ...enu 56 4 3 9 NVMe configuration submenu 57 4 3 10 SDIO configuration submenu 57 4 3 11 LVDS Configuration submenu 57 4 3 12 SuperI O configuration submenu 59 4 3 13 USB configuration submenu 59 4 3 14...

Page 5: ...ition 1 0 Last Edition 1 1 Author A R Reviewed by M B Copyright 2020 SECO S p A 5 Warranty Information and assistance RMA number request Safety Electrostatic Discharges RoHS compliance Terminology and...

Page 6: ...ne The RMA authorisation number must be put both on the packaging and on the documents shipped with the items which must include all the accessories in their original packaging with no signs of damage...

Page 7: ...ter it is possible to send the faulty product to the SECO Repair Centre In this case follow this procedure o Returned items must be accompanied by a RMA Number Items sent without the RMA number will b...

Page 8: ...ng RoHS compliant components and is manufactured on a lead free production line It is therefore fully RoHS compliant Always switch the power off and unplug the power supply unit before handling the bo...

Page 9: ...tween boards and digital displays GBE Gigabit Ethernet Gbps Gigabits per second GND Ground GPI O General purpose Input Output HEVC High Efficiency Video Coding a video compression standard also known...

Page 10: ...er SATA Serial Advance Technology Attachment a differential full duplex serial interface for Hard Disks SD Secure Digital a memory card type SDIO Secure Digital Input Output an evolution of the SD sta...

Page 11: ...thor A R Reviewed by M B Copyright 2020 SECO S p A 11 VP9 Successor to VP8 customized for video greater than 1080p WMV9 Series 9 of Windows Media Video a video compression format inlcuding native supp...

Page 12: ...ification pdf HDMI http www hdmi org index aspx I2C http www nxp com documents other UM10204_v5 pdf I2S https www sparkfun com datasheets BreakoutBoards I2SBUS pdf Intel Atom Apollo Lake family https...

Page 13: ...or A R Reviewed by M B Copyright 2020 SECO S p A 13 SM Bus http www smbus org specs UEFI http www uefi org USB 2 0 and USB OTG http www usb org developers docs usb_20_070113 zip USB 3 0 https usb org...

Page 14: ...Rev First Edition 1 0 Last Edition 1 1 Author A R Reviewed by M B Copyright 2020 SECO S p A 14 Introduction Technical Specifications Electrical Specifications Mechanical Specifications Supported Opera...

Page 15: ...tX12 OpenGL 4 3 OpenCL 2 0 OGL ES 3 0 and HW acceleration for video encoding and decoding of HEVC H 265 H 264 MVC VP8 VP9 JPEG MJPEG It is also possible the HW video decoding only of MPEG2 VC 1 and WM...

Page 16: ...l Channel 18 24bit LVDS interface HDMI or DP interface DP interface 2 x CSI interfaces Video Resolution HDMI eDP resolution up to 3840x2160 4K 60Hz DP resolution up to 4096x2160 60Hz LVDS resolution u...

Page 17: ...sumption must be intended as average value 30 seconds acquisition Independently by the SOC mounted onboard the following power consumptions are common to all boards Battery Backup power consumption 4...

Page 18: ...Also named 5V_DSW VDD_RTC Low current RTC circuit backup power 3V coin cell voltage coming from the edge card for supplying the RTC clock on the I MX 8M 3 3V_DSW 3 3 Always on voltage derived internal...

Page 19: ...fications components placed on bottom side of SM B69 will have a maximum height of 1 3mm Keep this value in mind when choosing the MXM connector s height if there is the need to place components on th...

Page 20: ...System Memory eMMC Drive Power section 5V_S 3 3V_RTC Intel Apollo Lake family SoC 2 x PCI e x1 FACTORY ALTERNATIVES FACTORY ALTERNATIVES NXP PTN3460 eDP to LVDS SM Bus Gigabit Ethernet 0 I2S HD Audio...

Page 21: ...SM B69 SM B69 User Manual Rev First Edition 1 0 Last Edition 1 1 Author A R Reviewed by M B Copyright 2020 SECO S p A 21 Introduction Connectors description...

Page 22: ...t 2020 SECO S p A 22 3 1 Introduction According to SMARC specifications all interfaces to the board are available through a single card edge connector TOP SIDE Card edge golden finger pin P1 Card edge...

Page 23: ...orted on the card edge connector For accurate signals description please consult the following paragraphs SMARC Golden Finger Connector CN4 TOP SIDE BOTTOM SIDE SIGNAL GROUP Type Pin name Pin nr Pin n...

Page 24: ...C N C P28 S29 PCIE_D_TX GBE I O GBE0_MDI0 P29 S30 PCIE_D_TX GBE I O GBE0_MDI0 P30 S31 GBE1_LINK_ACT N C P31 S32 PCIE_D_RX GND P32 S33 PCIE_D_RX SDIO_CARD I SDIO_WP P33 S34 GND SDIO_CARD I O SDIO_CMD...

Page 25: ...INTERFACE SPI_INTERFACE I O ESPI_IO_0 P57 S58 ESPI_RESET O SPI_INTERFACE SPI_INTERFACE I O ESPI_IO_1 P58 S59 USB5 I O USB GND P59 S60 USB I O USB USB I O USB0 P60 S61 GND USB I O USB0 P61 S62 USB3_SST...

Page 26: ...88 S89 GND PCI_e O PCIE_A_TX P89 S90 PCIE_B_TX O PCI_e PCI_e O PCIE_A_TX P90 S91 PCIE_B_TX O PCI_e GND P91 S92 GND DISPLAY O HDMI_D2 P92 S93 DP0_LANE0 O DISPLAY DISPLAY O HDMI_D2 P93 S94 DP0_LANE0 O D...

Page 27: ...LVDS1_3 O DISPLAY GND P120 S121 LVDS1_3 O DISPLAY MANAGEMENT I O I2C_PM_CK P121 S122 LCD1_BKLT_PWM O LCD_SUPPORT MANAGEMENT I O I2C_PM_DAT P122 S123 GPIO13 I O GPIO BOOT_SEL I BOOT_SEL0 P123 S124 GND...

Page 28: ...ER3_RX P141 S142 GPIO12 I O GPIO GND P142 S143 GND N C P143 S144 eDP0_HPD I DISPLAY N C P144 S145 WDT_TIME_OUT O WATCHDOG N C P145 S146 PCIE_WAKE I PCI_e N C P146 S147 VDD_RTC VDD_IN P147 S148 LID I M...

Page 29: ...Output LCD1_BKLT_EN Panel 1 Backlight Enable signal It can be used to turn On Off the backlight s lamps of a connected LVDS display 1 8V_RUN electrical level Output LCD1_BKLT_PWM This signal can be u...

Page 30: ...pported by the SOC For this reason considering that LVDS dual channel interfaces can be factory alternative on the same pins with eDP interface on SM B69 module can be implemented an eDP to LVDS bridg...

Page 31: ...VDS Channel 0 differential Clock OR the signals for Channel 0 are eDP eDP0_TX0 eDP0_TX0 eDP Channel 0 differential data pair 0 eDP0_TX1 eDP0_TX1 eDP Channel 0 differential data pair 1 eDP0_TX2 eDP0_TX...

Page 32: ...ill be not connected LVDS1_1 LVDS1_0 LVDS Channel 1 differential data pair 0 LVDS1_1 LVDS1_1 LVDS Channel 1 differential data pair 1 LVDS1_2 LVDS1_2 LVDS Channel 1 differential data pair 2 LVDS1_3 LVD...

Page 33: ...et of signals from the following two sets are present dependent on the factory board configuration EITHER the signals for the Channel are HDMI HDMI_D0 HDMI_D0 HDMI Output Differential Pair 0 HDMI_D1 H...

Page 34: ...ntial Pair 1 DP1_LANE2 DP1_LANE2 DP Channel 1 Output Differential Pair 2 DP1_LANE3 DP1_LANE3 DP Channel 1 Output Differential Pair 3 DP1_AUX DDC Clock line for DP Channel 1 Bidirectional signal 1 8V_R...

Page 35: ...data pair 3 DP0_HPD Hot Plug Detect Active high Input signal of 1 8V_S electrical level from carrier board down resistor DP0_AUX DDC Clock line for DP Channel 0 up resistor DP0_AUX DDC Data line for...

Page 36: ...to the Carrier board electrical level 1 8V_RUN I2C_CAM0_DAT I2C control interface data signal to configure the camera sensor for MIPI CSI 0 Bi Directional between the module to the Carrier board elec...

Page 37: ...us of Write Protect switch of the external SD card Since microSD car n designing carrier boards with microSD slots this signal must be tied to GND otherwise the OS will always consider the card as pro...

Page 38: ...ere is only one SPI device ESPI_IO_0 SPI channel 1 Master Data Input electrical level 1 8V_RUN ESPI_IO_1 SPI channel 1 Master Data Output electrical level 1 8V_RUN 3 2 1 9 Audio interface signals The...

Page 39: ...wo high speed UART with a maximum speed of 115 200 kb s or 3 6864Mb s depending on Industry standards In addition two additional UART are offered and managed by the Embedded controller MEC1705 from Mi...

Page 40: ...application If there isn t any explicit need of interfacing directly at 1 8V_DSW level for connection to standard serial ports commonly available like those offered by common PCs for example it is ma...

Page 41: ...disconnected Signal Low It must be tied to GND when USB Port 0 has to be set to work in Host mode When not driven USB Port 0 will work in Client mode USB1 USB1 Universal Serial Bus Port 2 0 2 differen...

Page 42: ...Copyright 2020 SECO S p A 42 USB3_SSRX USB3_SSRX USB 3 0 Port 5 Superspeed Receive differential pair For EMI ESD protection common mode chokes on USB data lines and clamping diodes on USB data and vol...

Page 43: ...K PCIE_B_REFCK PCI Express Reference Clock for lane 1 Differential Pair PCIE_B_RST Reset Signal that is sent from SMARC Module to a PCI e device available on the carrier board Active Low 3 3V_ALW elec...

Page 44: ...ential pair GBE0_MDI3 GBE0_MDI3 Media Dependent Interface MDI Transmit differential pair GBE0_LINK_ACT Ethernet controller activity indicator Active Low Output signal 3 3V_ALW electrical level GBE0_LI...

Page 45: ...on of Ethernet interface on the carrier board with TVS diodes specifically designed to protect sensitive components which are connected to high speed data and transmission lines from overvoltage cause...

Page 46: ...evel GPIO11 General Purpose I O 11 1 8V_DSW electrical level GPIO12 General Purpose I O 12 1 8V_DSW electrical level GPIO13 General Purpose I O 13 1 8V_DSW electrical level 3 2 1 17 Management pins A...

Page 47: ...Battery Charger Present input from the Carrier Board Input active low signal 3 3V_DSW electrical level with a 2k2 pull up resistor TEST Signals used to invoke from Carrier Board specific test functio...

Page 48: ...69 User Manual Rev First Edition 1 0 Last Edition 1 1 Author A R Reviewed by M B Copyright 2020 SECO S p A 48 Aptio setup Utility Main setup menu Advanced menu Chipset menu Security menu Boot menu Sav...

Page 49: ...rity Power Boot Select a setup item or a submenu and keys allows to change the field value of highlighted menu item F1 The F1 key allows displaying the General Help screen F2 Previous Values F3 F3 key...

Page 50: ...us Speed and memory configuration Only two options can be configured 4 2 1 System Date System Time Use this option to change the system time and date Highlight System Time or System Date using the Arr...

Page 51: ...Graphic Output protocol Network Stack Configuration See submenu Network Stack Settings CSM Configuration See submenu Compatibility Support Module CSM Configuration Enable Disable Option ROM NVMe Conf...

Page 52: ...Disables SHA 1 PCR Bank SHA256 PCR Bank Enabled Disabled Enables or Disables SHA256 PCR Bank Pending Operation None TPM Clear Schedule an Operation for the Security Device NTE your Computer will reboo...

Page 53: ...sables the Console redirection When enabled the following item will appear Console Redirection Settings See Submenu The settings specifies how the host and the remote computer which the user is using...

Page 54: ...Columns and Rows supported redirection Putty Keypad VT100 Intel Linux XTERMR6 SCO ESCN VT400 Select FunctionKey and KeyPad on Putty Redirection after BIOS POST Always Enabled BootLoader When BootLoade...

Page 55: ...ems will appear Power Limit 1 Clamp Mode Disabled Enabled When Power Limit 1 is Enabled enables or disables the Clamp Mode Power Limit 1 Power Auto 3 4 5 6 7 8 9 10 Power Limit 1 in Watts Auto will pr...

Page 56: ...ables the Compatibility Support Module CSM Support When enabled the following menu items will appear GateA20 Active Upon Request Always Upon Request GateA20 can be disabled using BIOS services Always...

Page 57: ...did Mode External Default Custom Select the source EDID Extended Display Identification Data to be used for the internal flat panel Depending on the setting chosen only some of the following option or...

Page 58: ...airs Swapping Enabled Disabled Enable or disable LVDS Differential pairs swapping Positive Negative Pairs Order Swapping Enabled Disabled Enable or disable channel differential pairs order swapping A...

Page 59: ...the IRQ line to assign to each Serial Port if enabled Menu Item Options Description Legacy USB Support Enabled Disabled Auto Enables Legacy USB Support AUTO Option disables legacy support if no USB d...

Page 60: ...35 Sets External PWM Frequency in Hertz Ext PWM DC 0 100 Sets external PWM Duty Cycle Ext Tacho Configuration 3 Wire 4 Wire Sets External Tachometric FAN Type LID_BTN Configuration Force Open Force Cl...

Page 61: ...al Trip Point 15 C 23 C 31 C 39 C 47 C 55 C 63 C 71 C 79 C 87 C 95 C 100 C 103 C 110 C 119 C 125 C This value controls the temperature of the ACPI Critical Trip Point the point in which the OS will sh...

Page 62: ...ce interrupts In Quiet Mode Host will wait for a SERIRQ slave to generate a request by driving the SERIRQ line low OS Selection Windows Android Win7 Intel Linux Select the Target OS Real Time Option R...

Page 63: ...decrease power consumption GTT Size 2 MB 4 MB 8 MB Select the GTT Graphics Translation Table Size Aperture Size 256 MB Use this item to set the total size of Memory that must be left to the GFX Engin...

Page 64: ...udio Support Enabled Disabled Enable Disable HD Audio Support HD Audio DSP Enabled Disabled Enable Disable HD Audio DSP Menu Item Options Description I2C 1 D22 F0 Disable PCI Mode ACPI Mode Enable Dis...

Page 65: ...Root Port 2 Internal LAN 1 PCIE Root Port 3 SMARC PCIE0 PCIE Root Port 4 SMARC PCIE1 PCIE Root Port 5 SMARC PCIE2 PCIE Root Port 6 SMARC PCIE3 Sets the parameters for each single PCI e Root Port Menu...

Page 66: ...upport Enabled Disabled Enable or Disable SCC eMMC Card Support Menu Item Options Description xHCI Pre Boot Driver Enable Disable Enables or Disable the support for XHCI Pre boot driver xHCI Mode Enab...

Page 67: ...hen power is re applied after a power failure G3 state In S0 State the System will boot directly as soon as power is applied IN S5 State the System keeps in power off state until power button is press...

Page 68: ...to modify Secure Boot Policy variables without full authentication Menu Item Options Provision Factory Default keys Enabled Disabled Provision factory default keys on next re boot only when System in...

Page 69: ...Place First Place Last Controls the placement of newly detected UEFI boot options Boot Mode Select LEGACY UEFI Select the boot mode between Legacy and UEFI Boot Option 1 Boot Option 2 Boot Option 3 Bo...

Page 70: ...nges and Reset Reset the system without saving any changes Save Changes Save the changes done so far to any of the setup options Discard Changes Discard the changes done so far to any of the setup opt...

Page 71: ...SM B69 SM B69 User Manual Rev First Edition 1 0 Last Edition 1 1 Author A R Reviewed by M B Copyright 2020 SECO S p A 71 Thermal Design...

Page 72: ...m but should be used only as a supplemental means of transferring heat to another dissipation system i e heat sinks fans heat pipes etc It is the customer s responsibility to design and apply an appli...

Page 73: ...M B69 User Manual Rev First Edition 1 0 Last Edition 1 1 Author A R Reviewed by M B Copyright 2020 SECO S p A 73 SECO S p A Via A Grandi 20 52100 Arezzo ITALY Ph 39 0575 26979 Fax 39 0575 350210 www s...

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