Q7-B03
Q7-B03 User Manual - Rev. First Edition: 1.0 - Last Edition: 1.1 - Author: S.B. - Reviewed by G.G. Copyright © 2017 SECO S.r.l.
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3.2.1.12
LPC interface signals
According to Qseven
®
specifications rel. 2.1, on the golden edge finger connector there are 8 pins that are used for implementation of Low Pin Count (LPC) Bus
interface.
The following signals are available:
LPC_AD[0÷3]: LPC address, command and data bus, bidirectional signal, +3.3V_S electrical level.
LPC_CLK: LPC Clock Output line, +3.3V_S electrical level. Since only a clock line is available, if it is necessary to connect more LPC devices on the carrier board,
then provide for a zero-delay clock buffer to connect all clock lines to the single clock output of Qseven
®
module.
LPC_FRAME#: LPC Frame indicator, active low output line, +3.3V_S electrical level. This signal is used to signal the start of a new cycle of transmission, or the
termination of existing cycles due to abort or time-out condition.
SERIRQ: LPC Serialised IRQ request, bidirectional line, +3.3V_S electrical level. This signal is used only by peripherals requiring Interrupt support.
3.2.1.13
SPI interface signals
The Intel
®
Bay Trail family of SOCs offers also one dedicated controller for Serial Peripheral Interface (SPI), which can be used for connection of EEPROMs and
Serial Flash devices. This interface does not support platform firmware (BIOS).
SPI interface supports master mode only can support speed up to 15Mbps.
Signals involved with SPI management are the following:
SPI_MOSI: SPI Master Out Slave In, Output from Qseven
®
module to SPI devices embedded on the Carrier Board. Electrical level +3.3V_S.
SPI_MISO: SPI Master In Slave Out, Input to Qseven
®
module from SPI devices embedded on the Carrier Board. Electrical level +3.3V_S.
SPI_CLK: SPI Clock Output to carrier board
’
s SPI embedded devices. Electrical level +3.3V_S.
SPI_CS0#: SPI Chip select #0, active low output signal (+3.3V_S electrical level).
SPI_CS1#: SPI Chip select #1, active low output signal (+3.3V_S electrical level).
Warning: Although the Qseven
®
specification states that pins 185-192 can be used for the implementation of the LPC bus or as 8 GPIOs, this
option is intended only for the manufacturers of the modules who are free to choose the option they deem more appropriate.
On the Q7-B03 module, the aforementioned pins have been dedicated to the LPC bus; use of these pins for different implementations other than
LPC (i.e. as GPIOs) is therefore not possible.
