Seco Qseven Q7-B03 User Manual Download Page 61

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Q7-B03

4.4.3

South Cluster Configuration submenu

4.4.3.1

HD Audio Configuration submenu

Menu Item

Options

Description

HD Audio Configuration

See submenu

HD Audio Configuration Settings

LPSS Configuration

See submenu

Low Power Sub System Configuration Settings

PCI Express Configuration

See submenu

PCI Express Configuration Settings

SATA Drives

See submenu

SATA Devices Configuration Setup options

SCC Configuration

See submenu

Storage Control Cluster Configuration Settings

USB Configuration

See submenu

USB configuration Settings

Miscellaneous Configuration

See submenu

Miscellaneous Settings

Menu Item

Options

Description

HD Audio Support

Enabled / Disabled

Enable / Disable HD Audio Support

Summary of Contents for Qseven Q7-B03

Page 1: ...Q7 B03 Qseven Rel 2 1 Compliant Module with the Intel Atom E39xx family Intel Celeron N3350 and Intel Pentium N4200 formerly code name Apollo Lake SoCs...

Page 2: ...any inaccuracies errors or omissions herein SECO S r l reserves the right to change precise specifications without prior notice to supply the best product possible For further information on this modu...

Page 3: ...13 Chapter 2 2 1 Introduction 14 2 2 Technical Specifications 15 2 3 Electrical Specifications 16 2 3 1 Power Rails meanings 16 2 3 2 Power Consumption 16 2 4 Mechanical Specifications 18 2 5 Block D...

Page 4: ...nfiguration submenu 53 4 3 10 SDIO configuration submenu 53 4 3 11 LVDS Configuration submenu 54 4 3 12 SuperI O configuration submenu 55 4 3 13 USB configuration submenu 56 4 3 14 Platform Trust tech...

Page 5: ...1 0 Last Edition 1 1 Author S B Reviewed by G G Copyright 2017 SECO S r l 5 Chapter 1 Warranty Information and assistance RMA number request Safety Electrostatic Discharges RoHS compliance Terminolog...

Page 6: ...A authorisation number must be put both on the packaging and on the documents shipped with the items which must include all the accessories in their original packaging with no signs of damage to or ta...

Page 7: ...ntre it is possible to send the faulty product to the SECO Repair Centre In this case follow this procedure o Returned items must be accompanied by a RMA Number Items sent without the RMA number will...

Page 8: ...high voltages caused by static electricity could damage some or all the devices and or components on board 1 6 RoHS compliance The Q7 B03 module is designed using RoHS compliant components and is man...

Page 9: ...eration DP Display Port a type of digital video display interface DVI Digital Visual interface a type of digital video display interface eDP embedded Display Port a type of digital video display inter...

Page 10: ...the installed OS SATA Serial Advance Technology Attachment a differential half duplex serial interface for Hard Disks SD Secure Digital a memory card type SDHC Secure Digital Host Controller or Secure...

Page 11: ...org index aspx I2C http www nxp com documents other UM10204_v5 pdf JTAG http standards ieee org develop wg Boundary_Scan_Architecture html LPC Bus http www intel com design chipsets industry lpc htm...

Page 12: ...right 2017 SECO S r l 12 UEFI http www uefi org USB 2 0 and USB OTG http www usb org developers docs usb_20_070113 zip USB 3 0 http www usb org developers docs usb_30_spec_070113 zip Intel Atom Pentiu...

Page 13: ...r Manual Rev First Edition 1 0 Last Edition 1 1 Author S B Reviewed by G G Copyright 2017 SECO S r l 13 Chapter 2 Introduction Technical Specifications Electrical Specifications Mechanical Specificati...

Page 14: ...OpenGL 4 3 OpenCL 1 2 OpenGLES 3 0 and HW acceleration for video encoding and decoding of HEVC H 265 H 264 JPEG MJPEG It is also possible the HW video decoding only of VP9 MPEG2 VC 1 and WMV9 This emb...

Page 15: ...ATA Gen3 channels SD interface Optional eMMC Drive soldered onboard USB 2 x USB 3 0 Host Port 6 x USB2 0 Host ports Networking Gigabit Ethernet interface Intel I210 or I211 Controller MAC PHY Audio H...

Page 16: ...h in ACPI s S0 Working and S3 Standby state Examples 1 5V_U 2 3 2 Power Consumption Q7 B03 module like all Qseven modules needs a carrier board for its normal working All connections with the external...

Page 17: ...1 042A 2 312A 1 128A 3 036A 1 168A 2 870A Video reproduction 720p power saving configuration 0 604A 1 048A 0 589A 0 966A 0 830A 1 875A 0 782A 1 52A 0 656A 1 195A Video reproduction 1080p power saving...

Page 18: ...rious connector heights for different carrier board applications needs Qseven specification suggests two connector heights 7 8mm and 7 5mm but it is also possible to use different connector heights al...

Page 19: ...LVDS Gigabit Ethernet PCI e interface 6 x USB 2 0 ports STMicroelectronics STM32F100R4 microcontroller eMMC Drive Intel Apollo Lake family SOC Intel Ethernet Controller I21x DDR3L System Memory DDR3L...

Page 21: ...interfaces to the board are available through a single card edge connector Moreover an additional Fan connector has been placed on the right side of the board in order to allow an easier connection of...

Page 22: ...lease consult the following paragraphs NOTE Even pins are available on top side of CPU board odd pins are available on bottom side of CPU board Please refer to board photos Qseven Golden Finger Connec...

Page 23: ...A N C 55 56 USB_OTG_PEN O USB PWR GND 57 58 GND PWR AUDIO O HDA_SYNC 59 60 SMB_CLK I O MISC AUDIO O HDA_RST 61 62 SMB_DAT I O MISC AUDIO O HDA_BCLK 63 64 SMB_ALERT I O MISC AUDIO I HDA_SDI 65 66 GP0_I...

Page 24: ...LVDS_A3 eDP0_TX3 115 116 LVDS_B3 O LVDS PWR GND 117 118 GND PWR LVDS O LVDS_A_CLK eDP0_AUX 119 120 LVDS_B_CLK O LVDS LVDS O LVDS_A_CLK eDP0_AUX 121 122 LVDS_B_CLK O LVDS LVDS eDP O LVDS_BLT_CTRL 123...

Page 25: ..._TX 173 174 PCIE1_RX I PCI E PCI E O PCIE1_TX 175 176 PCIE1_RX I PCI E UART I UART0_RX 177 178 UART0_CTS I UART PCI E O PCIE0_TX 179 180 PCIE0_RX I PCI E PCI E O PCIE0_TX 181 182 PCIE0_RX I PCI E PWR...

Page 26: ...ferential pair PCIE1_RX PCIE1_RX PCI Express lane 1 Receiving Input Differential pair PCIE2_TX PCIE2_TX PCI Express lane 2 Transmitting Output Differential pair PCIE2_RX PCIE2_RX PCI Express lane 2 Re...

Page 27: ...four root ports only and one PCI e root port is necessary to manage the Intel I21x Gigabit Ethernet controller For this reason it is not possible to manage the four PCI e lanes in the 4 PCI e x 1 conf...

Page 28: ...on of RS 232 transceiver for the Carrier board U1 SP3232ECY C1 1 C1 3 C2 4 C2 5 V 2 V 6 T1IN 11 T2IN 10 R1OUT 12 R2OUT 9 T1OUT 14 T2OUT 7 R1IN 13 R2IN 8 VCC 16 GND 15 P1 DB9 CONNECTOR 5 9 4 8 3 7 2 6...

Page 29: ...3V_A GBE_LINK100 Ethernet controller 100Mbps link indicator Active Low Output signal electrical level 3 3V_A GBE_LINK1000 Ethernet controller 1Gbps link indicator Active Low Output signal electrical l...

Page 30: ...l pair SATA_ACT Serial ATA Activity Led Active low output signal at 3 3V_S voltage 10nF AC series decoupling capacitors are placed on each line of SATA differential pairs On the carrier board these si...

Page 31: ...anaged by xHCI port 0 USB_SSTX1 USB_SSTX1 USB Super Speed Port 1 transmit differential pair managed by xHCI port 0 USB_0_1_OC USB Over Current Detect Input Active Low Input signal electrical level 3 3...

Page 32: ...chematics in the following page show an example of implementation on the Carrier Board In there USB ports 2 3 4 and 5 are carried out to standard USB 2 0 Type A receptacles USB 2 0 port 0 along with t...

Page 33: ...A USB_0_1_OC L8 BLM18KG471SN1 5V_A CN2 KMMX AB10 SMT1SB30TR VBUS 1 D 2 D 3 ID 4 GND 5 SSTX 6 SSTX 7 GND_D 8 SSRX 9 SSRX 10 SH 11 SH 12 SH 13 SH 14 SH 15 SH 16 JP2 JUMPER 1 2 USB_OTG_PEN R7 R 10K Q1 2N...

Page 34: ...te Protect switch of the external SD card Since microSD cards don t manage this signal it is important that when designing carrier boards with microSD slots this signal must be tied to GND otherwise t...

Page 35: ...tial clock LVDS_B0 LVDS_B0 LVDS Secondary Channel 0 differential data pair 0 LVDS_B1 LVDS_B1 LVDS Secondary Channel 0 differential data pair 1 LVDS_B2 LVDS_B2 LVDS Secondary Channel 0 differential dat...

Page 36: ...agement eDP0_TX0 eDP0_TX0 eDP channel differential data pair 0 eDP0_TX1 eDP0_TX1 eDP channel differential data pair 1 eDP0_TX2 eDP0_TX 2 eDP channel differential data pair 2 eDP0_TX3 eDP0_TX3 eDP chan...

Page 37: ...that can be used for implementation of HDMI_CEC Real usage of this signal depends on Q7 B03 dedicated API libraries HDMI_HPD Hot Plug Detect Input signal 3 3V_S electrical level signal active low with...

Page 38: ...Q1 2N7002 D2 IP4283CZ10 TBA 1 3 2 5 4 8 10 9 7 6 HDMI_CTRL_CLK HDMI_CTRL_DAT U1 SN74LVC1G14DBVR 2 3 4 5 L1 BLM18PG121SN1 TYPE A GND CN1 WHDM 19D5L1BF3U4W 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18...

Page 39: ...100k pull up resistor This signal was present on Qseven specifications until rev 1 2 while it has been deleted with Qseven specifications rev 2 1 since the Hot Plug signal for Display Port had been me...

Page 40: ...B 6 OE2 4 VCC 14 PAD 15 OE3 10 3A 9 3B 8 4A 12 OE4 13 4B 11 R6 R 100K C2 CC 100nF C3 CC 100nF R4 R 100K 3 3V_S 3 3V_S CAD R11 R 0 X R9 R 0 X DP_HPD R12 R 0 X CAD CAD DP_AUX DP_AUX HDMI_CTRL_CLK HDMI_C...

Page 41: ...signals The Intel Bay Trail family of SOCs offers also one dedicated controller for Serial Peripheral Interface SPI which can be used for connection of EEPROMs and Serial Flash devices This interface...

Page 42: ...unconnected if not used SUS_STAT Suspend status output active low 3 3V_A electrical voltage signal This output can be used to report to the devices on the carrier board that the module is going to en...

Page 43: ...put It is an active high signal 3 3V_S voltage managed by the STM32F100R4H6 microcontroller When this signal goes high active it reports out to the devices on the Carrier board that internal Watchdog...

Page 44: ...er Manual Rev First Edition 1 0 Last Edition 1 1 Author S B Reviewed by G G Copyright 2017 SECO S r l 44 Chapter 4 Aptio setup Utility Main setup menu Advanced menu Chipset menu Security menu Boot men...

Page 45: ...rity Power Boot Select a setup item or a submenu and keys allows to change the field value of highlighted menu item F1 The F1 key allows displaying the General Help screen F2 Previous Values F3 F3 key...

Page 46: ...us Speed and memory configuration Only two options can be configured 4 2 1 System Date System Time Use this option to change the system time and date Highlight System Time or System Date using the Arr...

Page 47: ...by Graphic Output protocol Network Stack Configuration See submenu Network Stack Settings CSM Configuration See submenu Compatibility Support Module CSM Configuration Enable Disable Option NVMe Config...

Page 48: ...Disables SHA 1 PCR Bank SHA256 PCR Bank Enabled Disabled Enables or Disables SHA256 PCR Bank Pending Operation None TPM Clear Schedule an Operation for the Security Device NTE your Computer will reboo...

Page 49: ...Hybernate OS S4 Sleep State This option may be not effective with some OS ACPI Sleep State Suspend Disabled S3 Suspend to RAM Select the highest ACPI Sleep state the system will enter when the SUSPEN...

Page 50: ...icates the beginning The standard setting is 1 stop bit Communication with slow devices may require more than 1 stop bit Flow Control None Hardware RTS CTS Flow Control can prevent data loss from buff...

Page 51: ...sensor trips either core the PROCHOT will be driven If bi direction is enabled external agents can drive PROCHOT to throttle the processor Thermal Monitor Disabled Enabled Enables or disables the Ther...

Page 52: ...ard mouse storage under UEFI and DOS environment When set to UEFI only then it will support exclusively UEFI environment Menu Item Options Description Network Stack Enabled Disabled Enables or disable...

Page 53: ...te the trap right away POSTPONED execute the trap during legacy boot Boot option filter UEFI and Legacy Legacy only UEFI only This option controls Legacy UEFI ROMs priority Network Stack Do not launch...

Page 54: ...Blank 1 4095 Horizontal Blanking in pixels equals to Horizontal Total Horizontal Active Horizontal Front Porch Horizontal Black Porch Vertical Active 1 4095 Vertical Addressable Video in pixels a k a...

Page 55: ...P N Pairs Swapping Enabled Disabled Enable or disable LVDS Differential pairs swapping Positive Negative Pairs Order Swapping Enabled Disabled Enable or disable channel differential pairs order swappi...

Page 56: ...uld be claimed by XHCI driver USB Mass Storage Driver Support Enabled Disabled Enables or disables USB Mass Storage Driver Support USB Transfer time out 1 sec 5 sec 10 sec 20 sec Sets the time out val...

Page 57: ...Sets external PWM Duty Cycle Ext Tacho Configuration 3 Wire 4 Wire Sets External Tachometric FAN Type LID_BTN Configuration Force Open Force Closed Normal Polarity Inverted Polarity Configures the LI...

Page 58: ...al Trip Point 15 C 23 C 31 C 39 C 47 C 55 C 63 C 71 C 79 C 87 C 95 C 100 C 103 C 110 C 119 C 125 C This value controls the temperature of the ACPI Critical Trip Point the point in which the OS will sh...

Page 59: ...Q Mode Quiet Mode Continuous Mode Select Serial IRQ Mode In continuous mode the host will continually check for device interrupts In Quiet Mode Host will wait for a SERIRQ slave to generate a request...

Page 60: ...nabled Disabled Permits to enable the render standby features which allows the on board graphics entering in standby mode to decrease power consumption GTT Size 2 MB 4 MB 8 MB Select the GTT Graphics...

Page 61: ...S Configuration See submenu Low Power Sub System Configuration Settings PCI Express Configuration See submenu PCI Express Configuration Settings SATA Drives See submenu SATA Devices Configuration Setu...

Page 62: ...y available when LPSS I2C 2 is not disabled Select LPSS I2C 2 Speed HSUART 0 D24 F0 Disable PCI Mode ACPI Mode Enable Disable LPSS HS UART 0 Support This HSUART is not connected to anything but must b...

Page 63: ...ways disable the PCIe root port all the following items will disappear ASPM Disable L0s L1 L0sL1 Auto PCI Express Active State Power Management Settings L1 Substates Disabled L1 1 L1 2 L1 1 L1 2 PCI E...

Page 64: ...cy Override for PCH PCIe Disabled Always Disable the Override Auto default Maintains default BIOS flow Manual Manually enter the following override values Snoop Latency value 0 1023 LTR Snoop Latency...

Page 65: ...Card Support Menu Item Options Description xHCI Pre Boot Driver Enable Disable Enables or Disable the support for XHCI Pre boot driver xHCI Mode Enable Disable Once Disabled the xHCI Controller would...

Page 66: ...after a power failure G3 state Always ON the System will boot directly as soon as the power is applied Always OFF the system remain in power off State until power button is pressed Wake On Lan Enabled...

Page 67: ...ttempt Secure Boot Enabled Disabled Secure Boot is activated when the Platform Key PK is enrolled System Mode is User Deployed and CSM function is disabled Enter Audit Mode Enter Audit mode If a curre...

Page 68: ...i Image File System Image Allow the selected image to run in Secure Boot mode Enrol SHA256 Hash Certificates of the Image into Authorized Signature Database db Platform key Key Exchange Keys Authorize...

Page 69: ...I OS USB Support Disable Full Initial Partial Install Disabled all USB devices will not be available until after OS boot Partial Initial USB Mass Storage and Specific USB Port device will NOT be avail...

Page 70: ...nges and Reset Reset the system without saving any changes Save Changes Save the changes done so far to any of the setup options Discard Changes Discard the changes done so far to any of the setup opt...

Page 72: ...ke heatsinks fans heat pipes and so on Conversely heatsinks in some situation can represent the cooling solution Indeed when using Q7 B03 module it is necessary to consider carefully the heat generate...

Page 73: ...7 B03 User Manual Rev First Edition 1 0 Last Edition 1 1 Author S B Reviewed by G G Copyright 2017 SECO S r l 73 SECO Srl Via Calamandrei 91 52100 Arezzo ITALY Ph 39 0575 26979 Fax 39 0575 350210 www...

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