Rotec MDR-42, User Manual

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MDR-42 Technical Data
ROTEC technology - 38 -
9.5. CPU, CHIPSET and SUPER I/O
9.5.1. CPU
The central processing unit(CPU) consists of:

Mobile Intel
®
Pentium
®
M, which includes such features as:

Supports Intel® Architecture with Dynamic Execution

High performance, low-power core

On-die, primary 32-kbyte instruction cache and 32-kbyte write-back data cache

On-die, 1-Mbyte second level cache with Advanced Transfer Cache Architecture

Advanced Branch Prediction and Data Prefetch Logic

Streaming SIMD Extensions 2 (SSE2)

400-MHz, Source-Synchronous processor system bus

Advanced Power Management features including Enhanced Intel SpeedStep®
technology
9.5.2. Chipset
The chipset consists of:

Intel® 855GM (north bridge)

Intel® 82801DB (south bridge
9.5.3. Super I/O
The super I/O device is a Winbond 83627HF