RL78/G23
ELCL Multiple Parameter Monitoring Function
R01AN5615EJ0200 Rev.2.00
Page 35 of 42
Mar.24.22
Table 5-10 ELCL register settings (Logic cell block L3)
Register
Symbol
Register Name
Setting Description
ELL3SEL0
Event link L3 signal select
register 0
08H
Select the signal selected by ELISEL7 as the link
target of L3
ELL3SEL4
Event link L3 signal select
register 4
04H
Select the signal selected by ELISEL9 as the link
target of L3
ELL3SEL6
Event link L3 signal select
register 6
00H
No selection (fixed to 0)
ELL3LNK0
Event link L3 output select
register 0
0AH
Link target selected by ELL3SEL0 to set control
of flip-flop 0 in logic cell block L3
ELL3LNK4
Event link L3 output select
register 4
01H
Link target selected by ELL3SEL4 to set control
of flip-flop 1 in logic cell block L3
ELL3LNK6
Event link L3 output select
register 6
03H
Link target selected by ELL3SEL6 to clock of flip-
flop 0 and 1 in logic cell block L3
ELL3CTL
Logic cell block L3 control
register
C0H
Enable use of logic cell block L3 flip-flops 0 and 1
Figure 5-8 Setting of logic cells L3
ELL3SEL0
ELL3SELn
ELISEL7
ELISEL9
ELL3LNKn
ELL3CTL
L3F0
L3F1
ELL3SEL4
ELL3SEL6
L3F0 Output Signal
L3F1 Output Signal
