RL78/G23
ELCL Multiple Parameter Monitoring Function
R01AN5615EJ0200 Rev.2.00
Page 33 of 42
Mar.24.22
Table 5-8 ELCL register settings (Logic cell block L1)
Register
Symbol
Register Name
Setting Description
ELL1SEL0
Event link L1 signal select
register 0
07H
Select the signal selected by ELISEL6 as the link
target of L1
ELL1SEL1
Event link L1 signal select
register 1
08H
Select the signal selected by ELISEL7 as the link
target of L1
ELL1SEL2
Event link L1 signal select
register 2
09H
Select the signal selected by ELISEL8 as the link
target of L1
ELL1SEL3
Event link L1 signal select
register 3
0AH
Select the signal selected by ELISEL9 as the link
target of L1
ELL1LNK0
Event link L1 output select
register 0
01H
Link target selected by ELL1SEL0 to input 0 of
logic cell 0 in logic cell block L1
ELL1LNK1
Event link L1 output select
register 1
02H
Link target selected by ELL1SEL1 to input 1 of
logic cell 0 in logic cell block L1
ELL1LNK2
Event link L1 output select
register 2
03H
Link target selected by ELL1SEL2 to input 0 of
logic cell 1 in logic cell block L1
ELL1LNK3
Event link L1 output select
register 3
04H
Link target selected by ELL1SEL3 to input 1 of
logic cell 1 in logic cell block L1
ELL1CTL
Logic cell block L1 control
register
0AH
Logic cell 0 selects OR circuit
Logic cell 1 selects OR circuit
Figure 5-6 Setting of logic cells L1
L1L0
ELL1SEL0
ELL1SEL1
ELL1SEL2
ELL1SEL3
L1L1
ELL1SELn
ELISEL6
ELISEL7
ELISEL8
ELISEL9
ELL1LNKn
ELL1CTL
L1L0 Output Signal
L1L1 Output Signal