Renesas M3A-HS71, User Manual

Page: 32 / 82

Functional Overview
2.3.3 External SDRAM
Rev.1.01 2008.05.07 2-18
REJ11J0012-0101
2
Table 2.3.4 lists the example for bus state controller setting at 66.67 MHz operation for the SH7670 bus clock.
Table 2.3.4 Bus State Controller Setting (SDRAM Read/Write)
User Area Target Device Bus State Controller Setting
CS3 EDS2516APTA-75 CS3 space bus control register : CS3BCR
Initial value: H'36DB 0600
Recommended setting value : H'0000 4600 (at 32 bus width)
• Memory specification
TYPE[2:0] = B'100; SDRAM
• Data bus specification
BSZ[1:0] = B'11; 32 bit bus width
CS3 space wait control register: CS3WCR
Initial value: H'0000 0500, Recommended setting value: H'0000 2892
• Wait precharge completion cycle count
WTRP[1:0] = B'01; 1 cycle
• Number of wait cycles from ACTV to READ (A) /WRITE (A)
command
WTRCD[1:0] = B'10; 2 cycles
• Area 3CAS latency
A3CL[1:0] = B'01; 2 cycles
• Wait precharge start cycle count
TRWL[1:0] = B'10; 2 cycles
• Idle cycles between REF command/self refresh release and
ACTV/REF/MRS command
WTRC[1:0] = B'10; 5 cycles
SDRAM control register: SDCR
Initial value: H'0000 0000, Recommended setting value: H'0000 0811
• Refresh control
RFSH = B'1; Refresh is performed
• Refresh control
RMODE = B'0 ; Auto-refreshing
• Bank Active mode
BACTV = B'0; Auto-precharge mode
• Number of bits of row address for area 3
A3ROW[1:0] = B'01; 13 bits
• Number of bits of column address for area3
A3COL[1:0] = B'01; 9 bits
Refresh timer control/Status register: RTCSR
Initial value
：
H'0000 0000, Recommended setting value:H'A55A 0010
• Clock select
CKS[2:0] = B'010; B
φ
/16
• Refresh count
RRC[2:0] = B'000; Once
Refresh Time Constant Register: RTCOR
Initial value: H'0000 0000, Recommended setting value: H'A55A 0020
*The refresh request interval when clock select is set to B
φ
/16 is as
follows.
1 cycle: 240 nsec (66.67 MHz/16=4.17 MHz)
Refresh request intervals in the SDRAM: 7.8
μ
sec/time
7.8usec /240nsec = 32(0x20) cycle/ refresh counts