Renesas M3A-HS71, User Manual

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Functional Overview
2.3.3 External SDRAM
Rev.1.01 2008.05.07 2-17
REJ11J0012-0101
2
2.3.3 External SDRAM Interface
The SH7670 CPU board standard mounts two 32-Mbyte SDRAMs as external SDRAM. It uses the bus state
controller with on-chip SH7670 to control the SDRAM.
Accessing to SDRAM is 32-bit bus access.
Table 2.3.3 lists the SDRAM specification used on the SH7670 CPU board, and Figure 2.3.3 shows the SDRAM
interface block diagram.
Table 2.3.3 SDRAM Specification
Specification Content
Part Number EDS2516APTA-75
Configuration 32 Mbytes (16-bit bus width) × 2 pcs.
Capacity 64 Mbytes
Access Time 5.4ns
CAS Latency 2 (at bus clock 66.67 MHz)
Refresh Interval 8192 refresh cycles every 64 ms
Low Address A11- A0
Column Address A8 - A0
Number of Banks 4 bank operations controlled by BA0, BA1
Figure 2.3.3 External SDRAM Interface Block Diagram