Renesas M3A-HS71, User Manual

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Functional Overview
2.2.2 SH7670 Pin Function Used on SH7670 CPU Board
Rev.1.01 2008.05.07 2-5
REJ11J0012-0101
2
Table 2.2.3 SH7670 Pin Selection Used on SH7670 CPU Board (3)
Type Pin I/O Name
Function of SH7670 CPU Board
Destination to Connect
INTC IRQ I Interrupt
request
Interrupt request pin which can select level
and edge input.
Each IRQ pin is connected to the
followings.
• IRQ7#(PD07/IRQ7#/SDCLK)
• IRQ6#(PD06/IRQ6#/SDCMD)
• IRQ5#(PD05/IRQ5#/SDCD)
• IRQ4#(PD04/IRQ4#/SDWP)
• IRQ3#(PD03/IRQ3#/SDDATA3)
• IRQ2#(PD02/IRQ2#/SDDATA2)
• IRQ1#(PD01/IRQ1#/SDDATA1)
• IRQ0#(PD00/IRQ0#/SDDATA0)
• IRQ3(PB05/CS5#/CE1A#/IRQ3/TEND1)
• IRQ2(PB04/CE2A#/IRQ2/DACK1)
• IRQ1(PB03/CS6#/CE1B#/IRQ1/DREQ1)
• IRQ0(PB02/CE2B#/IRQ0)
• Connects to an extension connector
IRQ7#(J8-12)
IRQ6#(J8-13)
IRQ5#(J8-14)
IRQ4#(J8-15)
IRQ3#(J8-16)
IRQ2#(J8-17)
IRQ1#(J8-18)
IRQ0#(J8-19)
IRQ3(J8-11)
IRQ2(J9-6)
IRQ1(J9-7)
IRQ0(J9-8)
• Connects to push switch
IRQ0 (SW5)
• Connects to VBUS IRQ1(U8-2)
DMA
C
DREQ1
DREQ0
I DMA transfer
request
External DMA transfer request input pin
DREQ1(PB03/CS6#/CE1B#/IRQ1/DREQ1)
DREQ0(PF09/ST0_VLD/DREQ0)
• Connects to an extension connector
DREQ1(J9-7)
• Connects to ST connector
DREQ1(J7-16)
DACK1
DACK0
O
DMA transfer
request is
acknowledged
Request acknowledge output pin to
external DMA transfer request
DACK1(PB04/CE2A#/IRQ2/DACK1)
DACK0(PF10/ST0_SYC//DACK0)
• Connects to an extension connector
DACK1(J9-6)
• Connects to ST connector
DACK0(J7-15)
TEND1
TEND0
O
DMA transfer
completion
output
DMA transfer completion output signal
TEND1(PB05/CS5#/CE1A#/IRQ3/TEND1)
TEND0(PF11/ST0_PWM/TEND0)
• Connects to an extension connector
TEND1(J8-11)
• Connects to ST connector
TEND0(J7-17)
Ether CRS
I
Carrier sense Carrier sense pin
CRS(PC15/CRS)
Connects to PHY-LSI (U7-23)
COL
I
Collision Collision detection pin
COL(PC14/COL)
Connects to PHY-LSI (U7-1)
MII_TXD3
MII_TXD2
MII_TXD1
MII_TXD0
O
Sending data
４
-bit sending data pin
MII_TXD3(PC07/MII_TXD3)
MII_TXD2(PC06/MII_TXD2)
MII_TXD1(PC05/MII_TXD1)
MII_TXD0(PC04/MII_TXD0)
Connects to PHY-LSI
MII_TXD3(U7-3)
MII_TXD2(U7-4)
MII_TXD1(U7-5)
MII_TXD0(U7-6)
TX_EN
O
Sending
enable
Indicates that sending data is ready for
MII_TXD3-0
TX_EN(PC12/TX_EN)
Connects to PHY-LSI (U7-2)
TX_CLK I Sending clock Reference timing of TX_EN, TX_ER, and
MII_TXD3-0
TX_CLK(PC13/TX_CLK)
Connects to PHY-LSI (U7-7)
TX_ER O Sending error Pins notifying PHY-LSI of the error in
transmitting TX_ER(PC11/TX_ER)
Connects to an extension connector
(J11-6)
MII_RXD3
MII_RXD2
MII_RXD1
MII_RXD0
I
Receive data
４
-bit receiving data pin
MII_RXD3(PC03/MII_RXD3)
MII_RXD2(PC02/MII_RXD2)
MII_RXD1(PC01/MII_RXD1)
MII_RXD0(PC00/MII_RXD0)
Connects to PHY-LSI
MII_RXD3(U7-18)
MII_RXD2(U7-19)
MII_RXD1(U7-20)
MII_RXD0(U7-21)
RX_DV
I
Receive data
valid
Indicates that there is enabled receiving
data for MII_RXD3-0
RX_DV(PC08/RX_DV)
Connects to PHY-LSI (U7-22)