Renesas H8/38342, Hardware Manual

Page: 351 / 721

Section 9 Timers
Rev. 6.00 Aug 04, 2006 page 313 of 680
REJ09B0145-0600
3. Register Configuration
Table 9.17 shows the register configuration of the watchdog timer.
Table 9.17 Watchdog Timer Registers
Name Abbr. R/W Initial Value Address
Timer control/status register W TCSRW R/W H'AA H'FFB2
Timer counter W TCW R/W H'00 H'FFB3
Clock stop register 2 CKSTP2 R/W H'FF H'FFFB
Port mode register 3 PMR3 R/W H'00 H'FFCA
9.6.2 Register Descriptions
1. Timer Control/Status Register W (TCSRW)
Bit
Initial value
Read/Write
7
B6WI
1
R
6
TCWE
0
R/(W)
*
5
B4WI
1
R
4
TCSRWE
0
R/(W)
*
3
B2WI
1
R
0
WRST
0
R/(W)
*
2
WDON
0
R/(W)
*
1
B0WI
1
R
Note:
*
Write is permitted only under certain conditions, which are given in the descriptions of
the individual bits.
TCSRW is an 8-bit read/write register that controls write access to TCW and TCSRW itself,
controls watchdog timer operations, and indicates operating status.
Bit 7: Bit 6 write inhibit (B6WI)
Bit 7 controls the writing of data to bit 6 in TCSRW.
Bit 7
B6WI
Description
0 Bit 6 is write-enabled
1 Bit 6 is write-protected (initial value)
This bit is always read as 1. Data written to this bit is not stored.