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Section 6 ROM

Rev. 6.00 Aug 04, 2006 page 170 of 680
REJ09B0145-0600

6.5.4

Register Configuration

Table 6.6 lists the register configuration to control the flash memory when the built in flash
memory is effective.

Table 6.6

Register Configuration

Register Name

Abbreviation

R/W

Initial Value

Address

Flash memory control register 1

FLMCR1

R/W

H'00

H'F020

Flash memory control register 2

FLMCR2

R

H'00

H'F021

Flash memory power control register

FLPWCR

R/W

H'00

H'F022

Erase block register

EBR

R/W

H'00

H'F023

Flash memory enable register

FENR

R/W

H'00

H'F02B

Note: FLMCR1, FLMCR2, FLPWCR, EBR, and FENR are 8 bit registers. Only byte access is

enabled which are two-state access. These registers are dedicated to the product in which
flash memory is included. The product in which PROM or ROM is included does not have
these registers. When the corresponding address is read in these products, the value is
undefined. A write is disabled.

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Summary of Contents for H8/38342

Page 1: ...ok over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electron...

Page 2: ...t for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas...

Page 3: ...3844R H8 3845R H8 3846R H8 3847R H8 3847S Group H8 3844S H8 3845S H8 3846S H8 3847S H8 38347 Group H8 38342 H8 38343 H8 38344 H8 38345 H8 38346 H8 38347 H8 38447 Group H8 38442 H8 38443 H8 38444 H8 38...

Page 4: ...s a total system before making a final decision on the applicability of the information and products Renesas Technology Corp assumes no responsibility for any damage liability or other loss resulting...

Page 5: ...This manual is intended for users undertaking the design of an application system using the H8 3847R Group H8 3847S Group H8 38347 Group and H8 38447 Group Readers using this manual require a basic k...

Page 6: ...functions as an output pin 6 During a break the watchdog timer continues to operate Therefore an internal reset is generated if an overflow occurs during the break Related Material The latest informa...

Page 7: ...Rev 6 00 Aug 04 2006 page v of xxxvi Application Note Manual Title Document No H8 300L Series Application Note ADE 502 065...

Page 8: ...Rev 6 00 Aug 04 2006 page vi of xxxvi...

Page 9: ...the on chip pull up MOS for pin P24 is on during the reset period It turns off and normal operation resumes after the reset is cleared The pull up MOS is controlled by hardware it cannot be manipulate...

Page 10: ...ics Table 15 26 DC Characteristics 519 525 Table and notes amended Item Symbol Applicable Pins Ip Pull up MOS current P10 to P17 P24 6 P30 to P37 P50 to P57 P60 to P67 Notes 4 Except current which flo...

Page 11: ...tates Table D 1 Port States Overview 660 Table and notes amended Port Reset P27 to P20 High impedance 3 Notes 1 High level output when MOS pull up is in on state 2 Reset output from P32 pin only H8 38...

Page 12: ...Rev 6 00 Aug 04 2006 page x of xxxvi...

Page 13: ...44 2 3 1 Data Formats in General Registers 45 2 3 2 Memory Data Formats 46 2 4 Addressing Modes 47 2 4 1 Addressing Modes 47 2 4 2 Effective Address Calculation 49 2 5 Instruction Set 53 2 5 1 Data T...

Page 14: ...ontrol Registers 97 3 3 3 External Interrupts 107 3 3 4 Internal Interrupts 108 3 3 5 Interrupt Operations 108 3 3 6 Interrupt Response Time 113 3 4 Application Notes 114 3 4 1 Notes on Stack Area Use...

Page 15: ...r Watch Mode is Cleared 144 5 4 4 Notes on External Input Signal Changes before after Watch Mode 144 5 5 Subsleep Mode 145 5 5 1 Transition to Subsleep Mode 145 5 5 2 Clearing Subsleep Mode 145 5 6 Su...

Page 16: ...Register EBR 174 6 6 4 Flash Memory Power Control Register FLPWCR 175 6 6 5 Flash Memory Enable Register FENR 176 6 7 On Board Programming Modes 177 6 7 1 Boot Mode 178 6 7 2 Programming Erasing in Us...

Page 17: ...escription 213 8 3 3 Pin Function 217 8 3 4 Pin States 218 8 4 Port 3 219 8 4 1 Overview 219 8 4 2 Register Configuration and Description 219 8 4 3 Pin Functions 223 8 4 4 Pin States 225 8 4 5 MOS Inp...

Page 18: ...s 247 8 11 Port A 248 8 11 1 Overview 248 8 11 2 Register Configuration and Description 248 8 11 3 Pin Functions 250 8 11 4 Pin States 250 8 12 Port B 251 8 12 1 Overview 251 8 12 2 Register Configura...

Page 19: ...verview 294 9 5 2 Register Descriptions 296 9 5 3 Noise Canceler 301 9 5 4 Operation 302 9 5 5 Application Notes 306 9 5 6 Timer G Application Example 311 9 6 Watchdog Timer 312 9 6 1 Overview 312 9 6...

Page 20: ...R 411 11 2 2 PWM Data Registers U and L PWDRU PWDRL 413 11 2 3 Clock Stop Register 2 CKSTPR2 414 11 3 Operation 415 11 3 1 Operation 415 11 3 2 PWM Operation Modes 416 Section 12 A D Converter 417 12...

Page 21: ...AM and Display 444 13 3 3 Luminance Adjustment Function V0 Pin 452 13 3 4 Low Power Consumption LCD Drive System 453 13 3 5 Operation in Power Down Modes 457 13 3 6 Boosting the LCD Drive Power Supply...

Page 22: ...nverter Characteristics 510 15 6 5 LCD Characteristics 511 15 7 Absolute Maximum Ratings of H8 38347 Group and H8 38447 Group 513 15 8 Electrical Characteristics of H8 38347 Group and H8 38447 Group 5...

Page 23: ...Diagrams of Port 8 655 C 9 Block Diagram of Port 9 656 C 10 Block Diagram of Port A 657 C 11 Block Diagram of Port B 658 C 12 Block Diagram of Port C 659 Appendix D Port States in the Different Proce...

Page 24: ...a Formats 45 Figure 2 4 Memory Data Formats 46 Figure 2 5 Data Transfer Instruction Codes 56 Figure 2 6 Arithmetic Logic and Shift Instruction Codes 60 Figure 2 7 Bit Manipulation Instruction Codes 63...

Page 25: ...k Input Example 121 Figure 4 6 Typical Connection to 32 768 kHz 38 4 kHz Crystal Oscillator Subclock 122 Figure 4 7 Equivalent Circuit of 32 768 kHz 38 4 kHz Crystal Oscillator 122 Figure 4 8 Pin Conn...

Page 26: ...iming Waveforms 193 Figure 6 17 Auto Program Mode Timing Waveforms 194 Figure 6 18 Auto Erase Mode Timing Waveforms 196 Figure 6 19 Status Read Mode Timing Waveforms 197 Figure 6 20 Oscillation Stabil...

Page 27: ...atchdog Timer 312 Figure 9 18 Typical Watchdog Timer Operations Example 318 Figure 9 19 Block Diagram of Asynchronous Event Counter 321 Figure 9 20 Example of Software Processing when Using ECH and EC...

Page 28: ...on when Transmitting Using Multiprocessor Format 8 bit data multiprocessor bit 1 stop bit 399 Figure 10 24 Example of Multiprocessor Data Reception Flowchart 400 Figure 10 25 Example of Operation when...

Page 29: ...Each Duty Cycle A Waveform 455 Figure 13 16 Output Waveforms for Each Duty Cycle B Waveform 456 Figure 13 17 Connection of External Split Resistance 458 Figure 13 18 Connection to HD66100 460 Section...

Page 30: ...ure C 3 f 1 Port 3 Block Diagram Pin P31 H8 3847R Group and H8 3847S Group 645 Figure C 3 f 2 Port 3 Block Diagram Pin P31 H8 38347 Group and H8 38447 Group 646 Figure C 3 g Port 3 Block Diagram Pin P...

Page 31: ...Figure H 1 Bonding Pad Form 674 Figure H 2 Bonding Pad Form 675 Figure H 3 Bonding Pad Form 676 Appendix I Specifications of Chip Tray Figure I 1 Specifications of Chip Tray 677 Figure I 2 Specificat...

Page 32: ...58 Table 2 7 Shift Instructions 59 Table 2 8 Bit Manipulation Instructions 61 Table 2 9 Branching Instructions 65 Table 2 10 System Control Instructions 67 Table 2 11 Block Data Transfer Instruction 6...

Page 33: ...ry Read Mode 190 Table 6 16 AC Characteristics in Transition from Memory Read Mode to Another Mode 191 Table 6 17 AC Characteristics in Memory Read Mode 192 Table 6 18 AC Characteristics in Auto Progr...

Page 34: ...e 8 30 Port A Pin Functions 250 Table 8 31 Port A Pin States 250 Table 8 32 Port B Register 251 Table 8 33 Port C Register 252 Table 8 34 Register Configuration 253 Section 9 Timers Table 9 1 Timer Fu...

Page 35: ...n between n and Clock 366 Table 10 8 Maximum Bit Rate for Each Frequency Asynchronous Mode 367 Table 10 9 Examples of BRR Settings for Various Bit Rates Synchronous Mode 1 368 Table 10 9 Examples of B...

Page 36: ...89 Table 15 12 Serial Interface SCI1 Timing 492 Table 15 13 Serial Interface SCI3 1 SCI3 2 Timing 493 Table 15 14 A D Converter Characteristics 494 Table 15 15 LCD Characteristics 495 Table 15 16 Segm...

Page 37: ...CPU Instruction Set Table A 1 Instruction Set 544 Table A 2 Operation Code Map 552 Table A 3 Number of Cycles in Each Instruction 554 Table A 4 Number of Cycles in Each Instruction 555 Appendix E List...

Page 38: ...Rev 6 00 Aug 04 2006 page xxxvi of xxxvi...

Page 39: ...channels and an A D converter Together these functions make the H8 3847R Group H8 3847S Group H8 38347 Group and H8 38447 Group ideally suited for embedded applications in systems requiring low power...

Page 40: ...ith H8 300 CPU Instruction length of 2 bytes or 4 bytes Basic arithmetic operations between registers MOV instruction for data transfer between memory and registers Typical instructions Multiply 8 bit...

Page 41: ...dium speed mode Memory Large on chip memory H8 3842R H8 38342 H8 38442 16 Kbyte ROM 1 Kbyte RAM H8 3843R H8 38343 H8 38443 24 Kbyte ROM 1 Kbyte RAM H8 3844R H8 3844S H8 38344 H8 38444 32 Kbyte ROM 2 K...

Page 42: ...on of four internal clock signals or event input from external pin Provision for toggle output by means of compare match function Timer G 8 bit timer Count up timer with selection of four internal clo...

Page 43: ...using a resistance ladder 12 channel analog input pins Conversion time 31 or 62 per channel LCD controller driver LCD controller driver equipped with a maximum of 40 segment pins and four common pins...

Page 44: ...TFP 100B TFP 100G Die 48 K 2 K HD6433845R HD6433845S HD64338345 HD64338445 FP 100A H8 3845R only FP 100B TFP 100B TFP 100G Die 40 K 2 K HD6433844R HD6433844S HD64338344 HD64338444 HD64F38344 HD64F3844...

Page 45: ...r F Timer G Serial communication interface 3 1 Serial communication interface 1 Serial communication interface 3 2 14 bit PWM LCD controller driver WDT Asynchronous counter A D 10 bit V0 V1 V2 V3 PA3...

Page 46: ...T Asynchronous counter A D 10 bit V0 V1 V2 V3 PA3 COM4 PA2 COM3 PA1 COM2 PA0 COM1 P87 SEG32 P86 SEG31 P85 SEG30 P84 SEG29 P83 SEG28 P82 SEG27 P81 SEG26 P80 SEG25 P77 SEG24 P76 SEG23 P75 SEG22 P74 SEG2...

Page 47: ...version are given in table 1 2 The bonding pad location diagram of the H8 3847S Group Mask ROM version is shown in figure 1 5 The bonding pad coordinates of the H8 3847S Group Mask ROM version are gi...

Page 48: ...3 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 P91 SEG34 P92 SEG35 P93 SEG36 P94 SEG37 M P94 SEG37 P95 SEG38 DO P95 SEG38 P96 SEG39 CL2 P96 SEG39 P97 SEG40 CL1 P97...

Page 49: ...SEG3 P51 WKP1 SEG2 P50 WKP0 SEG1 PA0 COM1 PA1 COM2 PA2 COM3 PA3 COM4 VCC V0 V1 V2 V3 VSS CVCC P37 AEVL P36 AEVH P35 TXD31 P34 RXD31 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 P93 SEG...

Page 50: ...65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 27 26 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 99 100 9897 9695 9493 92 91 90 89 88 87 868584 83 82 81 80 79 78 77 76 X Y 0 0...

Page 51: ...84 6 P15 IRQ1 TMIC 2866 810 7 P16 IRQ2 2866 636 8 P17 IRQ3 TMIF 2866 462 9 X1 2866 288 10 X2 2866 116 11 VSS 2866 56 12 OSC2 2866 228 13 OSC1 2866 402 14 TEST 2866 576 15 RES 2866 749 16 P20 SCK1 2866...

Page 52: ...PA0 COM1 544 2931 43 P50 WKP0 SEG1 842 2931 44 P51 WKP1 SEG2 1069 2931 45 P52 WKP2 SEG3 1256 2931 46 P53 WKP3 SEG4 1641 2931 47 P54 WKP4 SEG5 1829 2931 48 P55 WKP5 SEG6 2017 2931 49 P56 WKP6 SEG7 264...

Page 53: ...2 P85 SEG30 2866 1694 73 P86 SEG31 2866 1882 74 P87 SEG32 2866 2070 75 P90 SEG33 2866 2367 76 P91 SEG34 2866 2931 77 P92 SEG35 2654 2931 78 P93 SEG36 1998 2931 79 P94 SEG37 M 1803 2931 80 P95 SEG38 DO...

Page 54: ...C0 AN8 1704 2931 97 PC1 AN9 1876 2931 98 PC2 AN10 2048 2931 99 PC3 AN11 2658 2931 100 AVSS 2866 2931 Note These values show the coordinates of the centers of pads The accuracy is 5 m The home point po...

Page 55: ...31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 99 100 98 97 96 95 94 92 93 90 91 89 88 87 86 85 84 83 82 81 80...

Page 56: ...451 6 P15 IRQ1 TMIC 1655 334 7 P16 IRQ2 1655 226 8 P17 IRQ3 TMIF 1655 122 9 X1 1655 37 10 X2 1655 48 11 VSS 1655 138 12 OSC2 1655 223 13 OSC1 1655 308 14 TEST 1655 393 15 RES 1655 478 16 P20 SCK1 165...

Page 57: ...2 PA0 COM0 197 1605 43 P50 WKP0 SEG1 421 1605 44 P51 WKP1 SEG2 528 1605 45 P52 WKP2 SEG3 635 1605 46 P53 WKP3 SEG4 742 1605 47 P54 WKP4 SEG5 849 1605 48 P55 WKP5 SEG6 957 1605 49 P56 WKP6 SEG7 1154 16...

Page 58: ...72 P85 SEG30 1655 853 73 P86 SEG31 1655 960 74 P87 SEG32 1655 1067 75 P90 SEG33 1655 1527 76 P91 SEG34 1466 1605 77 P92 SEG35 1230 1605 78 P93 SEG36 1145 1605 79 P94 SEG37 M 1060 1605 80 P95 SEG38 DO...

Page 59: ...PC0 AN8 879 1605 97 PC1 AN9 991 1605 98 PC2 AN10 1103 1605 99 PC3 AN11 1290 1605 100 AVSS 1523 1605 Note These values show the coordinates of the centers of pads The accuracy is 5 m The home point pos...

Page 60: ...67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 99 100 101 9897 9695 9493 92 91 90 89 88 87 86 8584 83 82 81 80 79 78 77 X Y...

Page 61: ...IRQ1 TMIC 2056 839 7 P16 IRQ2 2056 737 8 P17 IRQ3 TMIF 2056 635 9 X1 2056 533 10 X2 2056 431 11 VSS 2056 329 12 VSS 2056 193 13 OSC2 2056 106 14 OSC1 2056 20 15 TEST 2056 66 16 RES 2056 244 17 P20 SC...

Page 62: ...301 2295 43 PA0 COM1 441 2295 44 P50 WKP0 SEG1 604 2295 45 P51 WKP1 SEG2 775 2295 46 P52 WKP2 SEG3 883 2295 47 P53 WKP3 SEG4 1022 2295 48 P54 WKP4 SEG5 1147 2295 49 P55 WKP5 SEG6 1302 2295 50 P56 WKP...

Page 63: ...034 72 P84 SEG29 2056 1159 73 P85 SEG30 2056 1378 74 P86 SEG31 2056 1503 75 P87 SEG32 2056 1627 76 P90 SEG33 2056 1840 77 P91 SEG34 1777 2295 78 P92 SEG35 1530 2295 79 P93 SEG36 1302 2295 80 P94 SEG37...

Page 64: ...se values show the coordinates of the centers of pads The accuracy is 5 m The home point position is the chip s center and the center is located at half the distance between the upper and lower pads a...

Page 65: ...44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 X Y 0 0 Chip size 3 55mm 3 7...

Page 66: ...P14 IRQ4 ADTRG 1658 907 6 P15 IRQ1 TMIC 1658 751 7 P16 IRQ2 1658 653 8 P17 IRQ3 TMIF 1658 555 9 X1 1658 456 10 X2 1658 358 11 VSS 1658 232 12 OSC2 1658 88 13 OSC1 1658 11 14 TEST 1658 113 15 RES 1658...

Page 67: ...42 PA0 COM1 481 1767 43 P50 WKP0 SEG1 637 1767 44 P51 WKP1 SEG2 762 1767 45 P52 WKP2 SEG3 887 1767 46 P53 WKP3 SEG4 1012 1767 47 P54 WKP4 SEG5 1158 1767 48 P55 WKP5 SEG6 1245 1767 49 P56 WKP6 SEG7 133...

Page 68: ...1101 72 P85 SEG30 1658 1226 73 P86 SEG31 1658 1351 74 P87 SEG32 1658 1475 75 P90 SEG33 1658 1613 76 P91 SEG34 1500 1767 77 P92 SEG35 1290 1767 78 P93 SEG36 1202 1767 79 P94 SEG37 1066 1767 80 P95 SEG...

Page 69: ...ow the coordinates of the centers of pads The accuracy is 5 m The home point position is the chip s center and the center is located at half the distance between the upper and lower pads and left and...

Page 70: ...it for a CVcc pin Vcc pin in the H8 3847S Group VSS 11 33 14 36 Input Ground All VSS pins should be connected to the system power supply 0 V AVCC 87 90 Input Analog power supply This is the power supp...

Page 71: ...See section 4 Clock Pulse Generators for a connection example This function is only available on the H8 38347 Group and H8 38447 Group System control RES 15 18 Input Reset When this pin is driven low...

Page 72: ...Input Timer F event input This is an event input pin for input to the timer F counter TMOFL 2 5 Output Timer FL output This is an output pin for waveforms generated by the timer FL output compare fun...

Page 73: ...is used pins P24 P25 P26 and P27 are reserved for use exclusively by the emulator and therefore cannot be accessed by the user With the F ZTAT version pull up pin P24 to high level to cancel a reset...

Page 74: ...output pin Serial communi cation interface SCI SCK1 16 19 I O SCI1 clock I O This is the SCI1 clock I O pin RXD31 28 31 Input SCI3 1 receive data input This is the SCI31 data input pin TXD31 29 32 Ou...

Page 75: ...e segment This function is not implemented in the H8 38347 Group and H8 38447 Group CL2 81 84 Output LCD shift clock This is the display data shift clock output pin for external expansion of the segme...

Page 76: ...Section 1 Overview Rev 6 00 Aug 04 2006 page 38 of 680 REJ09B0145 0600...

Page 77: ...eneral registers Instruction set with 55 basic instructions including Multiply and divide instructions Powerful bit manipulation instructions Eight addressing modes Register direct Register indirect R...

Page 78: ...r operation modes SLEEP instruction for transfer to low power operation Note These values are at 8 MHz 2 1 2 Address Space The H8 300L CPU supports an address space of up to 64 Kbytes for storing prog...

Page 79: ...general registers and control registers 7 0 7 0 15 0 PC R0H R1H R2H R3H R4H R5H R6H R7H R0L R1L R2L R3L R4L R5L R6L R7L SP SP Stack pointer PC Program counter CCR Condition code register Carry flag Ov...

Page 80: ...as the stack pointer as indicated in figure 2 2 SP R7 points to the top of the stack Lower address side H 0000 Upper address side H FFFF Unused area Stack area SP R7 Figure 2 2 Stack Pointer 2 2 2 Co...

Page 81: ...B W or CMP W instruction is executed the H flag is set to 1 if there is a carry or borrow at bit 11 and is cleared to 0 otherwise Bit 4 User Bit U Can be used freely by the user Bit 3 Negative Flag N...

Page 82: ...tware by the first instruction executed after a reset 2 3 Data Formats The H8 300L CPU can process 1 bit data 4 bit BCD data 8 bit byte data and 16 bit word data Bit manipulation instructions operate...

Page 83: ...data RnH 7 6 5 4 3 2 1 0 Don t care 7 0 1 bit data RnL MSB LSB Don t care Don t care 7 0 Byte data RnH Byte data RnL Word data Rn 4 bit BCD data RnH 4 bit BCD data RnL Legend RnH RnL MSB LSB Upper by...

Page 84: ...pplies to instruction codes Data Format 7 6 5 4 3 2 1 0 Address Data Type 7 0 Address n MSB LSB MSB LSB Upper 8 bits Lower 8 bits MSB LSB CCR CCR MSB LSB MSB LSB Address n Even address Odd address Eve...

Page 85: ...d 8 PC 8 Memory indirect aa 8 1 Register Direct Rn The register field of the instruction specifies an 8 or 16 bit general register containing the operand Only the MOV W ADD W SUB W CMP W ADDS SUBS MUL...

Page 86: ...aa 16 The MOV B and bit manipulation instructions can use 8 bit absolute addresses The MOV B MOV W JMP and JSR instructions can use 16 bit absolute addresses For an 8 bit absolute address the upper 8...

Page 87: ...pecified address See section 2 3 2 Memory Data Formats for further information 2 4 2 Effective Address Calculation Table 2 2 shows how effective addresses are calculated in each of the addressing mode...

Page 88: ...its of register indicated by rm 0 15 Register indirect with displacement d 16 Rn op rm rn 8 7 3 4 0 15 op rm 7 6 3 4 0 15 disp op rm 7 6 3 4 0 15 Register indirect with post increment Rn op rm 7 6 3 4...

Page 89: ...immediate data aa 16 op 8 7 0 15 op 0 15 IMM op disp 7 0 15 Program counter relative d 8 PC 6 7 0 15 PC contents 0 15 0 15 abs H FF 8 7 0 15 0 15 abs op xx 16 op 8 7 0 15 IMM Immediate xx 8 8 Sign ex...

Page 90: ...g Mode and Instruction Format Effective Address Calculation Method Effective Address EA 8 Memory indirect aa 8 op 8 7 0 15 Memory contents 16 bits 0 15 abs H 00 8 7 0 15 Legend rm rn op disp IMM abs R...

Page 91: ...L SHLR ROTL ROTR ROTXL ROTXR 8 Bit manipulation BSET BCLR BNOT BTST BAND BIAND BOR BIOR BXOR BIXOR BLD BILD BST BIST 14 Branch Bcc 2 JMP BSR JSR RTS 5 System control RTE SLEEP LDC STC ANDC ORC XORC NO...

Page 92: ...ition code register N N negative flag of CCR Z Z zero flag of CCR V V overflow flag of CCR C C carry flag of CCR PC Program counter SP Stack pointer IMM Immediate data disp Displacement Addition Subtr...

Page 93: ...mediate data to a general register The Rn Rn d 16 Rn aa 16 xx 16 Rn and Rn addressing modes are available for word data The aa 8 addressing mode is available for byte data only The R7 and R7 modes req...

Page 94: ...Rn disp 15 0 8 7 op rm rn Rm Rn or Rn Rm 15 0 8 7 op rn abs aa 8 Rn 15 0 8 7 op rn aa 16 Rn abs 15 0 8 7 op rn IMM xx 8 Rn 15 0 8 7 op rn xx 16 Rn IMM 15 0 8 7 op rn PUSH POP Legend op rm rn disp abs...

Page 95: ...ster INC DEC B Rd 1 Rd Increments or decrements a general register by 1 ADDS SUBS W Rd 1 Rd Rd 2 Rd Adds or subtracts 1 or 2 to or from a general register DAA DAS B Rd decimal adjust Rd Decimal adjust...

Page 96: ...cal AND operation on a general register and another general register or immediate data OR B Rd Rs Rd Rd IMM Rd Performs a logical OR operation on a general register and another general register or imm...

Page 97: ...ize Function SHAL SHAR B Rd shift Rd Performs an arithmetic shift operation on general register contents SHLL SHLR B Rd shift Rd Performs a logical shift operation on general register contents ROTL RO...

Page 98: ...P ADDX SUBX Rm Legend op rm rn IMM Operation field Register field Immediate data 15 0 8 7 op rn ADDS SUBS INC DEC DAA DAS NEG NOT 15 0 8 7 op rn MULXU DIVXU rm 15 0 8 7 rn IMM ADD ADDX SUBX CMP XX 8 o...

Page 99: ...data or the lower three bits of a general register BTST B bit No of EAd Z Tests a specified bit in a general register or memory and sets or clears the Z flag accordingly The bit number is specified b...

Page 100: ...No of EAd C Copies a specified bit in a general register or memory to the C flag BILD B bit No of EAd C Copies the inverse of a specified bit in a general register or memory to the C flag The bit num...

Page 101: ...x 3 rn 0 0 0 0 0 0 0 IMM 15 0 8 7 op 0 Operand Bit No register indirect Rn register direct Rm rn 0 0 0 0 0 0 0 rm op 15 0 8 7 op Operand Bit No absolute aa 8 immediate xx 3 abs 0 0 0 0 IMM op op 15 0...

Page 102: ...ddress Immediate data 15 0 8 7 op IMM rn Operand Bit No register direct Rn immediate xx 3 BIAND BIOR BIXOR BILD BIST 15 0 8 7 op 0 Operand Bit No register indirect Rn immediate xx 3 rn 0 0 0 0 0 0 0 I...

Page 103: ...escription Condition BRA BT Always true Always BRN BF Never false Never BHI High C Z 0 BLS Low or same C Z 1 BCC BHS Carry clear high or same C 0 BCS BLO Carry set low C 1 BNE Not equal Z 0 BEQ Equal...

Page 104: ...n field Register field Displacement Absolute address 15 0 8 7 op cc disp Bcc 15 0 8 7 op rm 0 JMP Rm 0 0 0 15 0 8 7 op JMP aa 16 abs 15 0 8 7 op abs JMP aa 8 15 0 8 7 op disp BSR 15 0 8 7 op rm 0 JSR...

Page 105: ...wn mode See section 5 Power Down Modes for details LDC B Rs CCR IMM CCR Moves immediate data or general register contents to the condition code register STC B CCR Rd Copies the condition code register...

Page 106: ...tion Figure 2 10 shows its object code format Table 2 11 Block Data Transfer Instruction Instruction Size Function EEPMOV If R4L 0 then repeat R5 R6 R4L 1 R4L until R4L 0 else next Block transfer inst...

Page 107: ...Section 2 CPU Rev 6 00 Aug 04 2006 page 69 of 680 REJ09B0145 0600 Legend op Operation field 15 0 8 7 op op Figure 2 10 Block Data Transfer Instruction Code...

Page 108: ...or three states The cycle differs depending on whether access is to on chip memory or to on chip peripheral modules 2 6 1 Access to On Chip Memory RAM ROM Access to on chip memory takes place in two s...

Page 109: ...his means that for accessing word data two instructions must be used Figures 2 12 and 2 13 show the on chip peripheral module access cycle Two state access to on chip peripheral modules T1 state Bus c...

Page 110: ...n chip peripheral modules T1 state Bus cycle Internal address bus Internal read signal Internal data bus read access Internal write signal Read data Address Internal data bus write access T2 state T3...

Page 111: ...tion state program halt state and exception handling state The program execution state includes active high speed or medium speed mode and subactive mode In the program halt state there are a sleep hi...

Page 112: ...chronized by the system clock The CPU executes successive program instructions at reduced speed synchronized by the system clock The CPU executes successive program instructions at reduced speed synch...

Page 113: ...nchronized with the system clock in active mode high speed and medium speed and with the subclock in subactive mode See section 5 Power Down Modes for details on these modes 2 7 3 Program Halt State I...

Page 114: ...n in figure 2 16 1 that of the H8 3843R H8 38343 and H8 38443 in figure 2 16 2 that of the H8 3844R H8 3844S H8 38344 and H8 38444 in figure 2 16 3 that of the H8 3845R H8 3845S H8 38345 and H8 38445...

Page 115: ...0029 H 002A H 3FFF H F740 H F75F H F780 H FB7F H FF90 H FFFF Interrupt vector area On chip ROM 16 Kbytes 16384 bytes 1024 bytes On chip RAM Internal I O registers 112 bytes Not used Not used Not used...

Page 116: ...0029 H 002A H 5FFF H F740 H F75F H F780 H FB7F H FF90 H FFFF Interrupt vector area On chip ROM 24 Kbytes 24576 bytes 1024 bytes On chip RAM Internal I O registers 112 bytes Not used Not used Not used...

Page 117: ...4F38444 Flash Memory Version On chip ROM 32 Kbytes 32768 bytes 2048 bytes On chip RAM Internal I O registers 112 bytes Firmware for on chip emulator 1 Internal I O registers Not used Not used Not used...

Page 118: ...9 H 002A H 9FFF H F740 H F75F H F780 H FF7F H FF90 H FFFF Interrupt vector area On chip ROM 40 Kbytes 40960 bytes 2048 bytes On chip RAM Internal I O registers 112 bytes Not used Not used Not used LCD...

Page 119: ...9 H 002A H BFFF H F740 H F75F H F780 H FF7F H FF90 H FFFF Interrupt vector area On chip ROM 48 Kbytes 49152 bytes 2048 bytes On chip RAM Internal I O registers 112 bytes Not used Not used Not used LCD...

Page 120: ...F38447 Flash Memory Version On chip ROM 61440 bytes 2048 bytes On chip RAM Internal I O registers 112 bytes Firmware for on chip emulator 1 Internal I O registers Not used Not used Work area for progr...

Page 121: ...Access to Internal I O Registers Internal data transfer to or from on chip modules other than the ROM and RAM areas makes use of an 8 bit data width If word access is attempted to these areas the foll...

Page 122: ...20 bytes Internal I O registers 112 bytes Access Word Byte 2 2 2 3 2 3 2 2 States 2048 bytes H FFA8 to H FFAF H 0000 H 0029 H 002A H 7FFF H F740 H F753 H F780 H FF7F H FF90 H FFFF H FF98 to H FF9F No...

Page 123: ...pulation in Two Registers Assigned to the Same Address Example 1 timer load register and timer counter Figure 2 18 shows an example in which two timer registers share the same address When a bit manip...

Page 124: ...evel signal at P36 The remaining pins P35 to P30 are output pins and output low level signals In this example the BSET instruction is used to change pin P30 to high level output A Prior to executing B...

Page 125: ...he CPU sets bit 0 of the read data to 1 changing the PDR3 data to H 41 Finally the CPU writes this value H 41 to PDR3 completing execution of BSET As a result of this operation bit 0 in PDR3 becomes 1...

Page 126: ...nipulation in a Register Containing a Write only Bit Example 3 BCLR instruction executed designating port 3 control register PCR3 As in the examples above P37 and P36 are input pins with a low level s...

Page 127: ...ata to 0 changing the data to H FE Finally this value H FE is written to PCR3 and BCLR instruction execution ends As a result of this operation bit 0 in PCR3 becomes 0 making P30 an input port However...

Page 128: ...3 1 0 0 0 0 0 0 0 RAM0 0 0 1 1 1 1 1 0 Table 2 12 lists the pairs of registers that share identical addresses Table 2 13 lists the registers that contain write only bits Table 2 12 Registers with Shar...

Page 129: ...trol register 3 PCR3 H FFE6 Port control register 4 PCR4 H FFE7 Port control register 5 PCR5 H FFE8 Port control register 6 PCR6 H FFE9 Port control register 7 PCR7 H FFEA Port control register 8 PCR8...

Page 130: ...uction It moves the number of bytes specified by R4L from the address specified by R5 to the address specified by R6 R5 R5 R4L R6 R6 R4L When setting R4L and R6 make sure that the final destination ad...

Page 131: ...rview A reset is the highest priority exception The internal state of the CPU and the registers of the on chip peripheral modules are initialized 3 2 2 Reset Sequence As soon as the RES pin goes low a...

Page 132: ...g vector address H 0000 2 Program start address 3 First instruction of program 2 3 2 1 Reset cleared Figure 3 1 Reset Sequence 3 2 3 Interrupt Immediately after Reset After a reset if an interrupt wer...

Page 133: ...the interrupt sources their priorities and their vector addresses When more than one interrupt is requested the interrupt with the highest priority is processed The interrupts have the following feat...

Page 134: ...nous counter overflow 12 H 0018 to H 0019 Timer C Timer C overflow or underflow 13 H 001A to H 001B Timer FL Timer FL compare match Timer FL overflow 14 H 001C to H 001D Timer FH Timer FH compare matc...

Page 135: ...R W H 00 H FFF9 Wakeup edge select register WEGR R W H 00 H FF90 Note Write is enabled only for writing of 0 to clear a flag 1 IRQ Edge Select Register IEGR Bit Initial value Read Write 7 1 6 1 5 1 4...

Page 136: ...ng of pin IRQ2 Bit 2 IEG2 Description 0 Falling edge of IRQ2 pin input is detected initial value 1 Rising edge of IRQ2 pin input is detected Bit 1 IRQ1 edge select IEG1 Bit 3 selects the input sensing...

Page 137: ...or disables timer A overflow interrupt requests Bit 7 IENTA Description 0 Disables timer A interrupt requests initial value 1 Enables timer A interrupt requests Bit 6 SCI1 interrupt enable IENS1 Bit 6...

Page 138: ...R W 2 IENTFL 0 R W 1 IENTC 0 R W IENR2 is an 8 bit read write register that enables or disables interrupt requests Bit 7 Direct transfer interrupt enable IENDT Bit 7 enables or disables direct transfe...

Page 139: ...verflow interrupt requests Bit 3 IENTFH Description 0 Disables timer FH interrupt requests initial value 1 Enables timer FH interrupt requests Bit 2 Timer FL interrupt enable IENTFL Bit 2 enables or d...

Page 140: ...quest Register 1 IRR1 Bit Initial value Read Write 7 IRRTA 0 R W 6 IRRS1 0 R W 5 1 4 IRRI4 0 R W 3 IRRI3 0 R W 0 IRRI0 0 R W 2 IRRI2 0 R W 1 IRRI1 0 R W Note Only a write of 0 for flag clearing is pos...

Page 141: ...it is cleared by writing 0 initial value 1 Setting condition When pin IRQn is designated for interrupt input and the designated signal edge is input n 4 to 0 5 Interrupt Request Register 2 IRR2 Bit In...

Page 142: ...AD Bit 6 IRRAD Description 0 Clearing condition When IRRAD 1 it is cleared by writing 0 initial value 1 Setting condition When A D conversion is completed and ADSF is cleared to 0 in ADSR Bit 5 Reserv...

Page 143: ...ition When IRRTFL 1 it is cleared by writing 0 initial value 1 Setting condition When TCFL and OCRFL match in 8 bit timer mode Bit 1 Timer C interrupt request flag IRRTC Bit 1 IRRTC Description 0 Clea...

Page 144: ...in IWPR is set to 1 A flag is not cleared automatically when the corresponding interrupt is accepted Flags must be cleared by writing 0 Bits 7 to 0 Wakeup interrupt request flags IWPF7 to IWPF0 Bit n...

Page 145: ...dling is initiated the I bit is set to 1 in CCR Vector number 9 is assigned to interrupts WKP7 to WKP0 All eight interrupt sources have the same vector number so the interrupt handling routine must di...

Page 146: ...ng the I bit to 1 in CCR When internal interrupt handling is initiated the I bit is set to 1 in CCR Vector numbers from 20 to 10 are assigned to these interrupts Table 3 2 shows the order of priority...

Page 147: ...rrupt is accepted after processing of the current instruction is completed both PC and CCR are pushed onto the stack The state of the stack at this time is shown in figure 3 4 The PC value pushed onto...

Page 148: ...saved I 1 I 0 Program execution state No Yes Yes No Legend PC CCR I Program counter Condition code register I bit of CCR IEN0 1 No Yes IENDT 1 No Yes IRRDT 1 No Yes Branch to interrupt handling routi...

Page 149: ...L CCR SP Upper 8 bits of program counter PC Lower 8 bits of program counter PC Condition code register Stack pointer Notes CCR CCR PCH PCL 1 2 PC shows the address of the first instruction to be execu...

Page 150: ...s Instruction is not executed Address is saved as PC contents becoming return address 2 4 Instruction code not executed 3 Instruction prefetch address Instruction is not executed 5 SP 2 6 SP 4 7 CCR 8...

Page 151: ...s after an interrupt request flag is set until the first instruction of the interrupt handler is executed Table 3 4 Interrupt Wait States Item States Total Waiting time for completion of executing ins...

Page 152: ...a program to crash An example is shown in figure 3 6 PC PC R1L PC SP SP SP H FEFC H FEFD H FEFF H L L MOV B R1L R7 SP set to H FEFF Stack accessed beyond SP BSR instruction Contents of PC are lost H L...

Page 153: ...e observed When an external interrupt pin function is switched by rewriting the port mode register that controls pins IRQ4 to IRQ0 WKP7 to WKP0 the interrupt request flag may be set to 1 at the time t...

Page 154: ...bit IEG0 0 When PMR3 bit IRQ0 is changed from 1 to 0 while pin IRQ0 is low and IEGR bit IEG0 1 IWPR IWPF7 When PMR5 bit WKP7 is changed from 0 to 1 while pin WKP7 is low IWPF6 When PMR5 bit WKP6 is c...

Page 155: ...not occur CCR I bit 1 Set port mode register bit Execute NOP instruction Interrupts masked Another possibility is to disable the relevant interrupt in interrupt enable register 1 After setting the po...

Page 156: ...8 set the value of R1L to B 11111101 Example of a malfunction When flags are cleared with multiple instructions other flags might be cleared during execution of the instructions even though they are...

Page 157: ...ator Subclock divider 1 2 1 4 1 8 System clock divider System clock pulse generator Subclock pulse generator Note H8 38347 Group and H8 38447 Group only Prescaler S 13 bits Prescaler W 5 bits OSC OSC...

Page 158: ...consult with the resonator manufacturer when selecting a resonator model 1 2 C1 C2 OSC OSC R 1 M 20 f Rf Figure 4 2 Typical Connection to Crystal Oscillator 2 Connecting a Ceramic Oscillator Figure 4...

Page 159: ...ted as close as possible to pins OSC1 and OSC2 OSC OSC C1 C2 Signal A Signal B 2 1 To be avoided Figure 4 4 Board Design of Oscillator Circuit 4 External Clock Input Method Connect an external clock s...

Page 160: ...rystal oscillator as shown in figure 4 6 Follow the same precautions as noted under 3 notes on board design for the system clock in section 4 2 X X C1 C2 1 2 C C 15 pF typ 1 2 Note Circuit constants s...

Page 161: ...as shown in figure 4 8 X X 1 2 Open GND Figure 4 8 Pin Connection when not Using Subclock 3 External Clock Input H8 3847R Group and H8 3847S Group Connect the external clock to the X1 pin and leave t...

Page 162: ...Group Frequency Subclock w Duty 45 to 55 4 Notes on H8 38347 and H8 38447 In the H8 38347 and H8 38447 the subclock oscillator input pin is controlled by the EXCL bit in the PMR2 register When EXCL is...

Page 163: ...the system clock pulse generator stops Prescaler S also stops and is initialized to H 0000 The CPU cannot read or write prescaler S The output from prescaler S is shared by timer A timer C timer F tim...

Page 164: ...exceeding its maximum rating Vss TEST OSC1 OSC2 Vss X2 X1 P17 Figure 4 10 Example of Crystal and Ceramic Oscillator Element Arrangement Figure 4 11 1 shows an example measuring circuit with the negati...

Page 165: ...Resistance Measurement and Circuit Modification Suggestions 4 5 1 Definition of Oscillation Stabilization Wait Time Figure 4 12 shows the oscillation waveform OSC2 system clock and microcomputer opera...

Page 166: ...ts 6 to 4 in system control register 1 SYSCR1 Oscillation waveform OSC2 System clock Oscillation stabilization time Operating mode Standby mode watch mode or subactive mode Wait time Oscillation stabi...

Page 167: ...dium speed mode with an oscillator element connected to the system clock oscillator careful evaluation must be carried out on the installation circuit before deciding on the oscillation stabilization...

Page 168: ...4 Clock Pulse Generators Rev 6 00 Aug 04 2006 page 130 of 680 REJ09B0145 0600 If the same kind of erroneous operation occurs after a reset as after a state transition hold the RES pin low for a longer...

Page 169: ...operable on the system clock Sleep medium speed mode The CPU halts On chip peripheral functions operate at a frequency of 1 64 1 32 1 16 or 1 8 of the system clock frequency Subsleep mode The CPU halt...

Page 170: ...on Conditions 1 LSON MSON SSBY DTON 0 0 1 0 0 0 0 1 0 0 1 0 1 1 0 0 0 0 1 1 0 0 1 1 1 0 0 0 0 0 1 1 1 1 1 Don t care Mode Transition Conditions 2 1 Interrupt Sources Timer A Timer F Timer G interrupt...

Page 171: ...nctions Functions Functions 8 Timer C Retained Functions Retained 2 Functions Retained 2 Retained WDT Functions Retained 7 Retained Timer G Timer F Functions Retained 9 Functions Retained 2 Functions...

Page 172: ...R W 4 STS0 0 R W 3 LSON 0 R W 0 MA0 1 R W 2 1 1 MA1 1 R W SYSCR1 is an 8 bit read write register for control of the power down modes Upon reset SYSCR1 is initialized to H 07 Bit 7 Software standby SSB...

Page 173: ...1 1 Wait time 65 536 states 1 0 0 Wait time 131 072 states 1 0 1 Wait time 2 states External clock input mode 1 1 0 Wait time 8 states 1 1 1 Wait time 16 states Note When inputting the external clock...

Page 174: ...YSCR2 Bit Initial value Read Write 7 1 6 1 5 1 4 NESEL 1 R W 3 DTON 0 R W 0 SA0 0 R W 2 MSON 0 R W 1 SA1 0 R W SYSCR2 is an 8 bit read write register for power down mode control Bits 7 to 5 Reserved b...

Page 175: ...ep mode 1 When a SLEEP instruction is executed in active high speed mode a direct transition is made to active medium speed mode if SSBY 0 MSON 1 and LSON 0 or to subactive mode if SSBY 1 TMA3 1 and L...

Page 176: ...ON and DTON bits in SYSCR2 are also cleared to 0 In sleep mode CPU operation is halted but the on chip peripheral functions CPU register contents are retained 2 Transition to Sleep Medium Speed Mode T...

Page 177: ...de or from sleep medium speed mode to active medium speed mode Sleep mode is not cleared if the I bit of the condition code register CCR is set to 1 or the particular interrupt is disabled in the inte...

Page 178: ...er the time set in bits STS2 to STS0 in SYSCR1 has elapsed a stable system clock signal is supplied to the entire chip standby mode is cleared and interrupt exception handling starts Operation resumes...

Page 179: ...s operation may start before the standby time is over 5 3 4 Standby Mode Transition and Pin States When a SLEEP instruction is executed in active high speed mode or active medium speed mode while bit...

Page 180: ...al clock stops The case of falling edge capture is illustrated in figure 5 3 As shown in the case marked Capture not possible when an external input signal falls immediately after a transition to acti...

Page 181: ...ent signall External input signal Active high speed medium speed mode or subactive mode Active high speed medium speed mode or subactive mode Standby mode or watch mode Wait for oscillation to settle...

Page 182: ...he mode to which a transition is made depends on the settings of LSON in SYSCR1 and MSON in SYSCR2 If both LSON and MSON are cleared to 0 transition is to active high speed mode if LSON 0 and MSON 1 t...

Page 183: ...he same states as before the transition 5 5 2 Clearing Subsleep Mode Subsleep mode is cleared by an interrupt timer A timer C timer F timer G asynchronous counter SCI1 SCI3 2 SCI3 1 IRQ4 to IRQ0 WKP7...

Page 184: ...nterrupt enable register 5 6 2 Clearing Subactive Mode Subactive mode is cleared by a SLEEP instruction or by a low input at the RES pin Clearing by SLEEP instruction If a SLEEP instruction is execute...

Page 185: ...ctive Medium Speed Mode Active medium speed mode is cleared by a SLEEP instruction Clearing by SLEEP instruction A transition to standby mode takes place if the SLEEP instruction is executed while the...

Page 186: ...are cleared to 0 the MSON bit in SYSCR2 is set to 1 and the DTON bit in SYSCR2 is set to 1 a transition is made to active medium speed mode via sleep mode Direct transfer from active medium speed mode...

Page 187: ...ter the waiting time set in SYSCR1 bits STS2 to STS0 has elapsed 5 8 2 Direct Transition Times 1 Time for direct transition from active high speed mode to active medium speed mode A direct transition...

Page 188: ...g clock Notation tosc OSC clock cycle time tcyc System clock cycle time 3 Time for direct transition from subactive mode to active high speed mode A direct transition from subactive mode to active hig...

Page 189: ...when w 8 or 8 is selected as the CPU operating clock and wait time 8192 states Notation tosc OSC clock cycle time tw Watch clock cycle time tcyc System clock cycle time tsubcyc Subclock SUB cycle time...

Page 190: ...and operation of the module halts This state is identical to standby mode Module standby mode is set for a particular module by setting the corresponding bit to 0 in clock stop register 1 CKSTPR1 or...

Page 191: ...is cleared 0 A D converter is set to module standby mode S1CKSTP 1 SCI1 module standby mode is cleared 0 SCI1 is set to module standby mode S32CKSTP 1 SCI3 2 module standby mode is cleared 0 SCI3 2 is...

Page 192: ...e will stop with the interrupt request still pending In this situation interrupt processing will be repeated indefinitely unless interrupts are prohibited It is therefore necessary to ensure that no i...

Page 193: ...S H8 38346 and H8 38446 have 48 Kbytes of mask ROM and the H8 3847R H8 3847S H8 38347 and H8 38447 have 60 Kbytes of mask ROM on chip The ROM is connected to the CPU by a 16 bit data bus allowing high...

Page 194: ...6 1 shows a block diagram of the on chip ROM H 7FFE H 7FFF Internal data bus upper 8 bits Internal data bus lower 8 bits Even numbered address Odd numbered address H 7FFE H 0002 H 0000 H 0000 H 0002 H...

Page 195: ...level PB4 AN4 Low level PB5 AN5 PB6 AN6 High level 6 2 2 Socket Adapter Pin Arrangement and Memory Map A standard PROM programmer can be used to program the PROM A socket adapter is required for conve...

Page 196: ...HN27C101 32 pin 1 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 22 24 31 32 16 RES P60 P61 P62 P63 P64 P65 P66 P67 P87 P86 P85 P84 P83 P82 P81 P80 P70 P43 P72 P73 P74 P75 P76 P14...

Page 197: ...teed if this address area is read in PROM mode Therefore when programming with a PROM programmer be sure to specify addresses from H 0000 to H EDFF If programming is inadvertently performed from H EE0...

Page 198: ...ations for writing and reading are identical to those for the standard HN27C101 EPROM However page programming is not supported and so page programming mode must not be set A PROM programmer that only...

Page 199: ...25 V V 12 5 V 0 3 V CC PP Address 0 n 0 n 1 n PW Verify Write time tOPW 0 2n ms Last address Set read mode V 5 0 V 0 25 V V V CC PP CC Read all addresses End Error n 25 Address 1 address No Yes No Go...

Page 200: ...C Item Symbol Min Typ Max Unit Test Condition Input high level voltage EO7 to EO0 EA16 to EA0 OE CE PGM VIH 2 4 VCC 0 3 V Input low level voltage EO7 to EO0 EA16 to EA0 OE CE PGM VIL 0 3 0 8 V Output...

Page 201: ...F 2 130 s VPP setup time tVPS 2 s Programming pulse width tPW 0 19 0 20 0 21 ms PGM pulse width for overwrite programming tOPW 3 0 19 5 25 ms CE setup time tCES 2 s VCC setup time tVCS 2 s Data output...

Page 202: ...erify timing diagram Write Input data Output data Verify Address Data VPP VPP tAS tAH tDS tDH tDF tOE tOES tPW tOPW tVPS tVCS tCES VCC VCC CE PGM OE VCC 1 VCC Note topw is defined by the value shown i...

Page 203: ...adapter and chip are properly aligned If they are not the chip may be destroyed by excessive current flow Before programming be sure that the chip is properly mounted in the PROM programmer Avoid tou...

Page 204: ...6 shows the recommended screening procedure Program chip and verify programmed data Bake chip for 24 to 48 hours at 125 C to 150 C with power off Read and check program Install Figure 6 6 Recommended...

Page 205: ...ogramming capability The flash memory can be reprogrammed up to 1 000 times On board programming On board programming erasing can be done in boot mode in which the boot program built into the chip is...

Page 206: ...FENR Flash memory enable register FLMCR2 EBR FLPWCR FENR Flash memory Figure 6 7 Block Diagram of Flash Memory 6 5 3 Block Configuration Figure 6 8 shows the block configuration of flash memory The th...

Page 207: ...81 H 7F82 Programming unit 128 bytes Programming unit 128 bytes Programming unit 128 bytes Programming unit 128 bytes Programming unit 128 bytes 1 Kbyte Erase unit 1 Kbyte Erase unit 1 Kbyte Erase uni...

Page 208: ...ory control register 2 FLMCR2 R H 00 H F021 Flash memory power control register FLPWCR R W H 00 H F022 Erase block register EBR R W H 00 H F023 Flash memory enable register FENR R W H 00 H F02B Note F...

Page 209: ...Programming Erasing By setting this register the flash memory enters program mode erase mode program verify mode or erase verify mode Read the data in the state that bits 6 to 0 of this register are...

Page 210: ...Bit 4 Program Setup PSU This bit is to prepare for changing to program mode Set this bit to 1 before setting the P bit to 1 in FLMCR1 do not set SWE ESU EV PV E and P bits at the same time Bit 4 PSU...

Page 211: ...bit is to set changing to or cancelling erase mode do not set SWE ESU PSU EV PV and P bits at the same time Bit 1 E Description 0 Erase mode is cancelled initial value 1 When this bit is set to 1 whi...

Page 212: ...e 1 Indicates that an error has occurred during an operation on flash memory programming or erasing Bits 6 to 0 Reserved These bits are always read as 0 and cannot be modified 6 6 3 Erase Block Regist...

Page 213: ...0 0 Read Write R W FLPWCR enables or disables a transition to the flash memory power down mode when the LSI switches to subactive mode The power supply circuit can be read in the subactive mode althou...

Page 214: ...cess to the flash memory control registers FLMCR1 FLMCR2 EBR and FLPWCR Bit 7 Flash Memory Control Register Enable FLSHE This bit controls access to the flash memory control registers Bit 7 FLSHE Desc...

Page 215: ...ates before the reset ends When changing to boot mode the boot program built into this LSI is initiated The boot program transfers the programming control program from the externally connected host to...

Page 216: ...adjustment end indication H 00 has been received normally and transmit one H 55 byte to the chip If reception could not be performed normally initiate boot mode again by a reset Depending on the host...

Page 217: ...ts data H 55 when data H 00 is received and no error occurs Transmits number of bytes N of programming control program to be transferred as 2 byte data low order byte following high order byte Transmi...

Page 218: ...Figure 6 9 shows a sample procedure for programming erasing in user program mode Prepare a user program erase control program in accordance with the description in section 6 8 Flash Memory Programming...

Page 219: ...must be written to the extra addresses 3 Prepare the following data storage areas in RAM A 128 byte programming data area a 128 byte reprogramming data area and a 128 byte additional programming data...

Page 220: ...Read verify data Reprogram data computation Clear PV bit in FLMCR1 Clear SWE bit in FLMCR1 Increment address Programming failure Clear SWE bit in FLMCR1 Wait 100 s No Yes No Yes No Wait 100 s n 1000...

Page 221: ...1 1 Remains in erased state Table 6 12 Additional Program Data Computation Table Reprogram Data Verify Data Additional Program Data Comments 0 0 0 Additional program bit 0 1 1 No additional programmi...

Page 222: ...s b 0 Verify data can be read in word size from the address to which a dummy write was performed 6 If the read data is not erased successfully set erase mode again and repeat the erase erase verify se...

Page 223: ...sable WDT Read verify data Increment address Verify data all 1s Last address of block All erase block erased Set block start address as verify address H FF dummy write to verify address Wait 20 s Wait...

Page 224: ...fect setting the P or E bit in FLMCR1 does not cause a transition to program mode or erase mode By setting the erase block register EBR erase protection can be set for individual blocks When EBR is se...

Page 225: ...10 1 Socket Adapter The socket adapter converts the pin allocation of the F ZTAT device to that of the discrete flash memory HN28F101 The address of the on chip flash memory is H 0000 to H EFFF Figur...

Page 226: ...ogrammer Mode 1st Cycle 2nd Cycle Command Name Number of Cycles Mode Address Data Mode Address Data Memory read 1 n Write X H 00 Read RA Dout Auto program 129 Write X H 40 Write WA Din Auto erase 2 Wr...

Page 227: ...1 12 11 10 9 8 7 6 5 27 24 23 25 4 28 29 22 32 16 FWE A9 A16 A15 WE I O0 I O1 I O2 I O3 I O4 I O5 I O6 I O7 A0 A1 A2 A3 A4 A5 A6 A7 A8 OE A10 A11 A12 A13 A14 CE Vcc Vss 60 66 3 51 52 53 54 55 56 57 58...

Page 228: ...consecutive reads can be performed 2 In memory read mode command writes can be performed in the same way as in the command wait state 3 After powering on memory read mode is entered 4 Tables 6 14 to...

Page 229: ...6 13 Timing Waveforms for Memory Read after Memory Write Table 6 16 AC Characteristics in Transition from Memory Read Mode to Another Mode Conditions VCC 3 3 V 0 3 V VSS 0 V Ta 25 C 5 C Item Symbol M...

Page 230: ...ry Read Mode to Another Mode Table 6 17 AC Characteristics in Memory Read Mode Conditions VCC 3 3 V 0 3 V VSS 0 V Ta 25 C 5 C Item Symbol Min Max Unit Notes Access time tacc 20 s Figure 6 15 CE output...

Page 231: ...es 4 The lower 7 bits of the transfer address must be low If a value other than an effective address is input processing will switch to a memory write operation but a write error will be flagged 5 Mem...

Page 232: ...e tds 50 ns Write pulse width twep 70 ns Status polling start time twsts 1 ms Status polling access time tspa 150 ns Address setup time tas 0 ns Address hold time tah 60 ns Memory write time twrite 1...

Page 233: ...retained until the next command write As long as the next command write has not been performed reading is possible by enabling CE and OE 5 Table 6 19 shows the AC characteristics Table 6 19 AC Charact...

Page 234: ...d decision signal Figure 6 18 Auto Erase Mode Timing Waveforms 6 10 6 Status Read Mode 1 Status read mode is provided to identify the kind of abnormal end Use this mode when an abnormal end occurs in...

Page 235: ...ime tceh 0 ns CE setup time tces 0 ns Data hold time tdh 50 ns Data setup time tds 50 ns Write pulse width twep 70 ns OE output delay time toe 150 ns Disable delay time tdf 100 ns CE output delay time...

Page 236: ...rwise I O3 0 I O2 0 I O1 0 1 Over counting of writing or erasing 0 Otherwise I O0 0 1 Effective address error 0 Otherwise 6 10 7 Status Polling 1 The I O7 status polling flag indicates the operating s...

Page 237: ...sc1 5 ms Programmer mode setup time Tbmv 10 ms Vcc hold time Tdwn 0 ms tosc1 tbmv tdwn Vcc RES Auto program mode Auto erase mode Figure 6 20 Oscillation Stabilization Time Boot Program Transfer Time a...

Page 238: ...power down mode with the PDWND bit in FLPWCR When the flash memory returns to its normal operating state from power down mode or standby mode a period to stabilize the power supply circuits that were...

Page 239: ...3847S H8 38347 and H8 38447 have 2 Kbytes of high speed static RAM on chip The RAM is connected to the CPU by a 16 bit data bus allowing high speed 2 state access for both byte data and word data 7 1...

Page 240: ...Section 7 RAM Rev 6 00 Aug 04 2006 page 202 of 680 REJ09B0145 0600...

Page 241: ...PDR Ports 5 6 7 8 9 and A are also used as liquid crystal display segment and common pins selectable in 8 bit units Block diagrams of each port are given in Appendix C I O Port Block Diagrams Table 8...

Page 242: ...to SEG1 PMR5 LPCR Port 6 8 bit I O port MOS input pull up option P67 to P60 SEG16 to SEG9 Segment output SEG16 to SEG9 LPCR Port 7 8 bit I O port P77 to P70 SEG24 to SEG17 Segment output SEG24 to SEG1...

Page 243: ...3 3 2 1 4 Port 1 P1 TMOFH P1 TMOFL P1 TMOW 2 1 0 Figure 8 1 Port 1 Pin Configuration 8 2 2 Register Configuration and Description Table 8 2 shows the port 1 register configuration Table 8 2 Port 1 Re...

Page 244: ...rolling whether each of the port 1 pins P17 to P10 functions as an input pin or output pin Setting a PCR1 bit to 1 makes the corresponding pin an output pin while clearing the bit to 0 makes the pin a...

Page 245: ...ion switch IRQ3 This bit selects whether pin P17 IRQ3 TMIF is used as P17 or as IRQ3 TMIF Bit 7 IRQ3 Description 0 Functions as P17 I O pin initial value 1 Functions as IRQ3 TMIF input pin Note Rising...

Page 246: ...This bit selects whether pin P14 IRQ4 ADTRG is used as P14 or as IRQ4 ADTRG Bit 4 IRQ4 Description 0 Functions as P14 I O pin initial value 1 Functions as IRQ4 ADTRG input pin Note For details of ADTR...

Page 247: ...r pin P11 TMOFL is used as P11 or as TMOFL Bit 1 TMOFL Description 0 Functions as P11 I O pin initial value 1 Functions as TMOFL output pin Bit 0 P10 TMOW pin function switch TMOW This bit selects whe...

Page 248: ...ds on bits IRQ2 in PMR1 and bit PCR16 in PCR1 IRQ2 0 1 PCR16 0 1 Pin function P16 input pin P16 output pin IRQ2 input pin P15 IRQ1 TMIC The pin function depends on bit IRQ1 in PMR1 bits TMC2 to TMC0 i...

Page 249: ...CR1 TMOFL 0 1 PCR11 0 1 Pin function P11 input pin P11 output pin TMOFL output pin P10 TMOW The pin function depends on bit TMOW in PMR1 and bit PCR10 in PCR1 TMOW 0 1 PCR10 0 1 Pin function P10 input...

Page 250: ...n MOS input pull up function that can be controlled by software When a PCR1 bit is cleared to 0 setting the corresponding PUCR1 bit to 1 turns on the MOS input pull up for that pin The MOS input pull...

Page 251: ...m This should be considered when making connections to external circuitry Note that the mask ROM and ZTAT versions do not have this function P27 P26 P25 P24 P23 P22 SO1 P21 SI1 P20 SCK1 Port 2 Figure...

Page 252: ...0 PCR20 0 W 2 PCR22 0 W 1 PCR21 0 W PCR2 is an 8 bit register for controlling whether each of the port 2 pins P27 to P20 functions as an input pin or output pin Setting a PCR2 bit to 1 makes the corre...

Page 253: ...is always read as 1 and cannot be modified H8 38347 Group and H8 38447 Group Bit 7 P31 UD EXCL pin function switch EXCL This bit selects whether pin P31 UD EXCL is used as P31 UD or as EXCL When the p...

Page 254: ...1 I O pin initial value 1 Functions as SI1 input pin Bit 0 P20 SCK1 pin function switch SCK1 This bit selects whether pin P20 SCK1 is used as P20 or as SCK1 Bit 0 SCK1 Description 0 Functions as P20 I...

Page 255: ...ion Method P27 to P23 The pin function depends on the corresponding bit in PCR2 n 7 to 3 PCR2n 0 1 Pin function P2n input pin P2n output pin P22 SO1 The pin function depends on bit SO1 in PMR2 and bit...

Page 256: ...Active P27 to P25 High impedance P24 1 Pull up MOS on Retains previous state Retains previous state High impedance Retains previous state Functional Functional P24 2 P23 High impedance P22 SO1 P21 SI1...

Page 257: ...38447 Group 31 P3 RXD P3 SCK P3 RESO 1 4 3 2 31 31 P3 UD EXCL 2 P3 PWM 1 0 Figure 8 3 Port 3 Pin Configuration 8 4 2 Register Configuration and Description Table 8 8 shows the port 3 register configu...

Page 258: ...rolling whether each of the port 3 pins P37 to P30 functions as an input pin or output pin Setting a PCR3 bit to 1 makes the corresponding pin an output pin while clearing the bit to 0 makes the pin a...

Page 259: ...in the H8 38347 Group and H8 38447 Group Bit 7 P37 AEVL pin function switch AEVL This bit selects whether pin P37 AEVL is used as P37 or as AEVL Bit 7 AEVL Description 0 Functions as P37 I O pin initi...

Page 260: ...Q0 Bit 3 IRQ IRQ IRQ IRQ0 Description 0 Functions as P43 input pin initial value 1 Functions as IRQ0 input pin Bit 2 P32 RESO pin function switch RESO This bit selects whether pin P32 RESO is used as...

Page 261: ...nctions Table 8 9 Port 3 Pin Functions Pin Pin Functions and Selection Method P37 AEVL The pin function depends on bit SO1 in PMR3 and bit PCR32 in PCR3 AEVL 0 1 PCR37 0 1 Pin function P37 input pin P...

Page 262: ...Group H8 38447 Group The pin function depends on bit PCR32 in PCR3 P32 H8 38347 H8 38447 PCR32 0 1 Pin function P32 input pin P32 output pin H8 3847R Group H8 3847S Group The pin function depends on b...

Page 263: ...ional P32 RESO 2 Reset output P32 3 P31 UD 2 P31 UD EXCL 3 P30 PWM High impedance Notes 1 A high level signal is output when the MOS pull up is in the on state 2 Applies to H8 3847R Group and H8 3847S...

Page 264: ...8 11 Port 4 Registers Name Abbr R W Initial Value Address Port data register 4 PDR4 R W H F8 H FFD7 Port control register 4 PCR4 W H F8 H FFE7 1 Port Data Register 4 PDR4 Bit Initial value Read Write...

Page 265: ...ntrolling whether each of port 4 pins P42 to P40 functions as an input pin or output pin Setting a PCR4 bit to 1 makes the corresponding pin an output pin while clearing the bit to 0 makes the pin an...

Page 266: ...depends on bit TE in SCR3 2 bit SPC32 in SPCR and bit PCR42 in PCR4 SPC32 0 1 TE 0 1 PCR42 0 1 Pin function P42 input pin P42 output pin TXD32 output pin P41 RXD32 The pin function depends on bit RE i...

Page 267: ...3 shows the port 4 pin states in each operating mode Table 8 13 Port 4 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active P43 IRQ0 P42 TXD32 P41 RXD32 P40 SCK32 High impedance Retains...

Page 268: ...G4 P52 WKP2 SEG3 P51 WKP1 SEG2 P50 WKP0 SEG1 Port 5 Figure 8 5 Port 5 Pin Configuration 8 6 2 Register Configuration and Description Table 8 14 shows the port 5 register configuration Table 8 14 Port...

Page 269: ...or controlling whether each of the port 5 pins P57 to P50 functions as an input pin or output pin Setting a PCR5 bit to 1 makes the corresponding pin an output pin while clearing the bit to 0 makes th...

Page 270: ...pin P5n WKPn SEGn 1 is not used as SEGn 1 these bits select whether the pin is used as P5n or WKPn Bit n WKPn Description 0 Functions as P5n I O pin initial value 1 Functions as WKPn input pin n 7 to...

Page 271: ...Retains previous state High impedance Retains previous state Functional Functional Note A high level signal is output when the MOS pull up is in the on state 8 6 5 MOS Input Pull Up Port 5 has a built...

Page 272: ...65 SEG14 P64 SEG13 P63 SEG12 P62 SEG11 P61 SEG10 P60 SEG9 Port 6 Figure 8 6 Port 6 Pin Configuration 8 7 2 Register Configuration and Description Table 8 17 shows the port 6 register configuration Tab...

Page 273: ...read Upon reset PDR6 is initialized to H 00 2 Port Control Register 6 PCR6 Bit Initial value Read Write 7 PCR67 0 W 6 PCR66 0 W 5 PCR65 0 W 4 PCR64 0 W 3 PCR63 0 W 0 PCR60 0 W 2 PCR62 0 W 1 PCR61 0 W...

Page 274: ...is initialized to H 00 8 7 3 Pin Functions Table 8 18 shows the port 6 pin functions Table 8 18 Port 6 Pin Functions Pin Pin Functions and Selection Method P67 SEG16 to P60 SEG9 The pin function depe...

Page 275: ...a built in MOS pull up function that can be controlled by software When a PCR6 bit is cleared to 0 setting the corresponding PUCR6 bit to 1 turns on the MOS pull up for that pin The MOS pull up functi...

Page 276: ...SEG24 P76 SEG23 P75 SEG22 P74 SEG21 P73 SEG20 Port 7 P72 SEG19 P71 SEG18 P70 SEG17 Figure 8 7 Port 7 Pin Configuration 8 8 2 Register Configuration and Description Table 8 20 shows the port 7 registe...

Page 277: ...read Upon reset PDR7 is initialized to H 00 2 Port Control Register 7 PCR7 Bit Initial value Read Write 7 PCR7 0 W 6 PCR7 0 W 5 PCR7 0 W 4 PCR7 0 W 3 PCR7 0 W 0 PCR7 0 W 2 PCR7 0 W 1 PCR7 0 W 7 6 5 4...

Page 278: ...R7n in PCR7 and bits SGS3 to SGS0 in LPCR n 7 to 0 SGS3 to SGS0 00 01 1 PCR7n 0 1 Pin function P7n input pin P7n output pin SEGn 17 output pin Don t care 8 8 4 Pin States Table 8 22 shows the port 7 p...

Page 279: ...SEG32 P86 SEG31 P85 SEG30 P84 SEG29 P83 SEG28 Port 8 P82 SEG27 P81 SEG26 P80 SEG25 Figure 8 8 Port 8 Pin Configuration 8 9 2 Register Configuration and Description Table 8 23 shows the port 8 registe...

Page 280: ...e read Upon reset PDR8 is initialized to H 00 2 Port Control Register 8 PCR8 Bit Initial value Read Write 7 PCR8 0 W 6 PCR8 0 W 5 PCR8 0 W 4 PCR8 0 W 3 PCR8 0 W 0 PCR8 0 W 2 PCR8 0 W 1 PCR8 0 W 7 6 5...

Page 281: ...n in PCR8 and bits SGS3 to SGS0 in LPCR n 7 to 0 SGS3 to SGS0 000 001 01 1 PCR8n 0 1 Pin function P8n input pin P8n output pin SEGn 25 output pin Don t care 8 9 4 Pin States Table 8 25 shows the port...

Page 282: ...3 SEG36 P92 SEG35 P91 SEG34 P90 SEG33 Port 9 Note The CL1 CL2 DO and M functions are not implemented on the H8 38347 Group and H8 38447 Group Figure 8 9 Port 9 Pin Configuration 8 10 2 Register Config...

Page 283: ...read Upon reset PDR9 is initialized to H 00 2 Port Control Register 9 PCR9 Bit Initial value Read Write 7 PCR97 0 W 6 PCR96 0 W 5 PCR95 0 W 4 PCR94 0 W 3 PCR93 0 W 0 PCR90 0 W 2 PCR92 0 W 1 PCR91 0 W...

Page 284: ...put pin P96 SEG39 CL2 The pin function depends on bit PCR96 in PCR9 and bits SGX and SGS3 to SGS0 in LPCR SGS3 to SGS0 0000 Not 0000 0000 SGX 0 0 1 PCR96 0 1 Pin function P96 input pin P96 output pin...

Page 285: ...PCR9n 0 1 Pin function P9n input pin P9n output pin SEGn 33 output pin Don t care 8 10 4 Pin States Table 8 28 shows the port 9 pin states in each operating mode Table 8 28 Port 9 Pin States Pins Res...

Page 286: ...Registers Name Abbr R W Initial Value Address Port data register A PDRA R W H F0 H FFDD Port control register A PCRA W H F0 H FFED 1 Port Data Register A PDRA Bit Initial value Read Write 7 1 6 1 5 1...

Page 287: ...trols whether each of port A pins PA3 to PA0 functions as an input pin or output pin Setting a PCRA bit to 1 makes the corresponding pin an output pin while clearing the bit to 0 makes the pin an inpu...

Page 288: ...t pin PA2 output pin COM3 output pin PA1 COM2 The pin function depends on bit PCRA1 in PCRA and bits SGS3 to SGS0 SGS3 to SGS0 0000 Not 0000 PCRA1 0 1 Pin function PA1 input pin PA1 output pin COM2 ou...

Page 289: ...Register Configuration and Description Table 8 32 shows the port B register configuration Table 8 32 Port B Register Name Abbr R W Address Port data register B PDRB R H FFDE 1 Port Data Register B PDR...

Page 290: ...11 PC2 AN10 PC1 AN9 PC0 AN8 Port C Figure 8 12 Port C Pin Configuration 8 13 2 Register Configuration and Description Table 8 33 shows the port C register configuration Table 8 33 Port C Register Name...

Page 291: ...w With input pins RXD31 and RXD32 and output pins TXD31 and TXD32 the data can be handled in inverted form SCINV0 SCINV2 RXD31 RXD32 P34 RXD31 P41 RXD32 SCINV1 SCINV3 TXD31 TXD32 P35 TXD31 P42 TXD32 F...

Page 292: ...6 Reserved bits Bits 7 and 6 are reserved they are always read as 1 and cannot be modified Bit 5 P42 TXD32 pin function switch SPC32 This bit selects whether pin P42 TXD32 is used as P42 or as TXD32 B...

Page 293: ...in input data is to be inverted Bit 2 SCINV2 Description 0 RXD32 input data is not inverted initial value 1 RXD32 input data is inverted Bit 1 TXD31 pin output data inversion switch Bit 1 specifies wh...

Page 294: ...al If an I O pin not used by the user system is floating pull it up or down If an unused pin is an input pin handle it in one of the following ways Pull it up to VCC with an on chip pull up MOS Pull i...

Page 295: ...of 4 overflow periods Clock output 4 to 32 W W 4 to W 32 9 choices TMOW Timer C 8 bit timer Interval function Event counting function Up count down count selectable 4 to 8192 W 4 7 choices TMIC Up co...

Page 296: ...z crystal oscillator is connected or from the system clock can be output at the TMOW pin 1 Features Features of timer A are given below Choice of eight internal clock sources 8192 4096 2048 512 256 12...

Page 297: ...A IRRTA PSW PSS CWOSR Note Can be selected only when the prescaler W output W 128 is used as the TCA input clock Timer mode register A Timer counter A Timer A overflow interrupt request flag Prescaler...

Page 298: ...FFB0 Timer counter A TCA R H 00 H FFB1 Clock stop register 1 CKSTPR1 R W H FF H FFFA Subclock output select register CWOSR R W H FE H FF92 9 2 2 Register Descriptions 1 Timer Mode Register A TMA Bit I...

Page 299: ...be output in active mode and sleep mode A 32 768 kHz or 38 4 kHz signal divided by 32 16 8 or 4 can be output in active mode sleep mode and subactive mode w is output in all modes except the reset sta...

Page 300: ...as follows Description Bit 3 TMA3 Bit 2 TMA2 Bit 1 TMA1 Bit 0 TMA0 Prescaler and Divider Ratio or Overflow Period Function 0 0 0 0 PSS 8192 initial value Interval timer 1 PSS 4096 1 0 PSS 2048 1 PSS...

Page 301: ...t to 1 TCA is cleared by setting bits TMA3 and TMA2 of TMA to 11 Upon reset TCA is initialized to H 00 3 Clock Stop Register 1 CKSTPR1 S1CKSTP TFCKSTP TCCKSTP TACKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP...

Page 302: ...r Operation 1 Interval Timer Operation When bit TMA3 in timer mode register A TMA is cleared to 0 timer A functions as an 8 bit interval timer Upon reset TCA is cleared to H 00 and bit TMA3 is cleared...

Page 303: ...mode subactive mode and subsleep mode The 32 768 kHz or 38 4 kHz clock is output in all modes except the reset state 9 2 4 Timer A Operation States Table 9 4 summarizes the timer A operation states T...

Page 304: ...Choice of seven internal clock sources 8192 2048 512 64 16 4 W 4 or an external clock can be used to count external events An interrupt is requested when the counter overflows Up down counter switchi...

Page 305: ...RRTC PSS Timer mode register C Timer counter C Timer load register C Timer C overflow interrupt request flag Prescaler S Figure 9 2 Block Diagram of Timer C 3 Pin Configuration Table 9 5 shows the tim...

Page 306: ...H FFFA 9 3 2 Register Descriptions 1 Timer Mode Register C TMC Bit Initial value Read Write 7 TMC7 0 R W 6 TMC6 0 R W 5 TMC5 0 R W 4 1 3 1 0 TMC0 0 R W 2 TMC2 0 R W 1 TMC1 0 R W TMC is an 8 bit read w...

Page 307: ...ead as 1 and cannot be modified Bits 2 to 0 Clock select TMC2 to TMC0 Bits 2 to 0 select the clock input to TCC For external event counting either the rising or falling edge can be selected Bit 2 TMC2...

Page 308: ...set in TLC the IRRTC bit in IRR2 is set to 1 TCC is allocated to the same address as TLC Upon reset TCC is initialized to H 00 3 Timer Load Register C TLC Bit Initial value Read Write 7 TLC7 0 W 6 TL...

Page 309: ...alue 9 3 3 Timer Operation 1 Interval Timer Operation When bit TMC7 in timer mode register C TMC is cleared to 0 timer C functions as an 8 bit interval timer Upon reset TCC is initialized to H 00 and...

Page 310: ...e from 1 to 256 input clocks depending on the TLC value The clock sources up down control and interrupts in auto reload mode are the same as in interval mode In auto reload mode TMC7 1 when a new valu...

Page 311: ...etained Retained Note When w 4 is selected as the TCC internal clock in active mode or sleep mode since the system clock and internal clock are mutually asynchronous synchronization is maintained by a...

Page 312: ...e The approximate rate of occurrence in cases where the external event input is not synchronized with internal operation is defined by the following equation Approximate rate of occurrence P 30 ns tsu...

Page 313: ...by a compare match signal Two interrupt sources one compare match one overflow Can operate as two independent 8 bit timers timer FH and timer FL in 8 bit mode Timer FH 8 Bit Timer Timer FL 8 Bit Timer...

Page 314: ...CFH OCRFH TCSRF Comparator Comparator Match IRRTFH IRRTFL Legend TCRF TCSRF TCFH TCFL OCRFH OCRFL IRRTFH IRRTFL PSS Timer control register F Timer control status register F 8 bit timer counter FH 8 bi...

Page 315: ...utput TMOFL Output Timer FL toggle output pin 4 Register Configuration Table 9 9 shows the register configuration of timer F Table 9 9 Timer F Registers Name Abbr R W Initial Value Address Timer contr...

Page 316: ...e section 9 4 3 CPU Interface TCFH and TCFL are each initialized to H 00 upon reset a 16 bit mode TCF When CKSH2 is cleared to 0 in TCRF TCF operates as a 16 bit counter The TCF input clock is selecte...

Page 317: ...re each initialized to H FF upon reset a 16 bit mode OCRF When CKSH2 is cleared to 0 in TCRF OCRF operates as a 16 bit register OCRF contents are constantly compared with TCF and when both values matc...

Page 318: ...nitialized to H 00 upon reset Bit 7 Toggle output level H TOLH Bit 7 sets the TMOFH pin output level The output level is effective immediately after this bit is written Bit 7 TOLH Description 0 Low le...

Page 319: ...KSL2 Bit 1 CKSL1 Bit 0 CKSL0 Description 0 0 0 Counting on external event TMIF rising falling initial value 0 0 1 edge 0 1 0 0 1 1 Not available 1 0 0 Internal clock counting on 32 1 0 1 Internal cloc...

Page 320: ...upon reset Bit 7 Timer overflow flag H OVFH Bit 7 is a status flag indicating that TCFH has overflowed from H FF to H 00 This flag is set by hardware and cleared by software It cannot be set by softwa...

Page 321: ...er TCFH is cleared when TCFH and OCRFH match Bit 4 CCLRH Description 0 16 bit mode TCF clearing by compare match is disabled 8 bit mode TCFH clearing by compare match is disabled initial value 1 16 bi...

Page 322: ...EL Description 0 TCFL overflow interrupt request is disabled initial value 1 TCFL overflow interrupt request is enabled Bit 0 Counter clear L CCLRL Bit 0 selects whether TCFL is cleared when TCFL and...

Page 323: ...ead write registers but the CPU is connected to the on chip peripheral modules by an 8 bit data bus When the CPU accesses these registers it therefore uses an 8 bit temporary register TEMP In 16 bit m...

Page 324: ...esults in transfer of the data in TEMP to the upper register byte and direct transfer of the lower byte write data to the lower register byte Figure 9 4 shows an example in which H AA55 is written to...

Page 325: ...e CPU In access to OCRF when the upper byte is read the upper byte data is transferred directly to the CPU When the lower byte is read the lower byte data is transferred directly to the CPU Figure 9 5...

Page 326: ...d from four internal clocks or an external clock by means of bits CKSL2 to CKSL0 in TCRF OCRF contents are constantly compared with TCF and when both values match CMFH is set to 1 in TCSRF If IENTFH i...

Page 327: ...to 0 in TCRF TCF can increment on either the rising or falling edge of external event input External event edge selection is set by IEG3 in the interrupt controller s IEGR register An external event p...

Page 328: ...n in table 9 10 Table 9 10 Timer F Operation Modes Operation Mode Reset Active Sleep Watch Subactive Subsleep Standby Module Standby TCF Reset Functions Functions Functions Halted Functions Halted Fun...

Page 329: ...are match signal generation if the clock is stopped Compare match flag CMFH is set when all 16 bits match and a compare match signal is generated Compare match flag CMFL is set if the setting conditio...

Page 330: ...of w figure 9 7 In active high speed medium speed mode even if you cleared interrupt request flag during the term of validity of Interrupt factor generation signal same interrupt request flag is set f...

Page 331: ...2 1 Set interrupt handling routine time to more than time that calculated with 1 formula 2 Clear interrupt request flags IRRTFH IRRTFL at the end of interrupt handling routine 3 After read timer contr...

Page 332: ...noise in the input capture input signal can be eliminated by a noise canceler enabling accurate measurement of the input capture input signal duty cycle If input capture input is not set timer G func...

Page 333: ...gram Figure 9 8 shows a block diagram of timer G PSS TMG ICRGF TCG ICRGR Noise canceler Edge detector Level detector IRRTG w 4 TMIG NCS Legend TMG TCG ICRGF ICRGR IRRTG NCS PSS Timer mode register G T...

Page 334: ...GF ICRGF R H 00 H FFBD Input capture register GR ICRGR R H 00 H FFBE Clock stop register 1 CKSTPR1 R W H FF H FFFA 9 5 2 Register Descriptions 1 Timer Counter TCG TCG7 TCG2 TCG1 TCG0 TCG6 TCG5 TCG4 T...

Page 335: ...1 in IRR2 and if IENTG in IENR2 is 1 an interrupt request is sent to the CPU For details of the interrupt see section 3 3 Interrupts To ensure dependable input capture operation the pulse width of the...

Page 336: ...sources counter clear selection and edge selection for the input capture input signal interrupt request controls enabling of overflow interrupt requests and also contains the overflow flags TMG is ini...

Page 337: ...tial value 1 Setting condition Set when TCG overflows from H FF to H 00 Bit 5 Timer overflow interrupt enable OVIE Bit 5 selects enabling or disabling of interrupt generation when TCG overflows Bit 5...

Page 338: ...1 and 0 Clock select CKS1 CKS0 Bits 1 and 0 select the clock input to TCG from among four internal clock sources Bit 1 CKS1 Bit 0 CKS0 Description 0 0 Internal clock counting on 64 initial value 0 1 I...

Page 339: ...Latch Match detector Noise canceler output Sampling clock Input capture input signal Sampling clock t t Set by CKS1 and CKS0 Figure 9 9 Noise Canceler Block Diagram The noise canceler consists of five...

Page 340: ...an example of noise canceler timing In this example high level input of less than five times the width of the sampling clock at the input capture input pin is eliminated as noise Input capture input s...

Page 341: ...set in TMG If the OVIE bit in TMG is 1 when these bits are set IRRTG is set to 1 in IRR2 and if the IENTG bit in IENR2 is 1 timer G sends an interrupt request to the CPU For details of the interrupt s...

Page 342: ...F Input capture signal R Figure 9 11 Input Capture Input Timing without Noise Cancellation Function b With noise cancellation function When noise cancellation is performed on the input capture input...

Page 343: ...ignal TCG N 1 N N H XX N 1 Input capture register Figure 9 13 Timing of Input Capture by Input Capture Input 5 TCG Clear Timing TCG can be cleared by the rising edge falling edge or both edges of the...

Page 344: ...l clock in watch mode TCG and the noise canceler operate on the w 4 internal clock without regard to the subclock w 8 w 4 w 2 Note that when another internal clock is selected TCG and the noise cancel...

Page 345: ...ration 1 Goes from low level to low level Clock before switching Clock after switching Count clock TCG N N 1 Write to CKS1 and CKS0 2 Goes from low level to high level Clock before switching Clock bef...

Page 346: ...er Modification The following points should be noted when a port mode register is modified to switch the input capture function or the input capture input noise canceler function Switching input captu...

Page 347: ...e input pin the timer G input capture input signal is low Switching input capture input noise canceler function When performing noise canceler function switching by modifying NCS in port mode register...

Page 348: ...used at least five sampling clocks when the noise canceler is used before clearing the interrupt enable flag to 0 There are two ways of preventing interrupt request flag setting when the pin function...

Page 349: ...e high and low widths of the input capture input signal as absolute values For this purpose CCLR1 and CCLR0 should both be set to 1 in TMG Figure 9 16 shows an example of the operation in this case Co...

Page 350: ...mented by internal clock source 8192 or w 32 A reset signal is generated when the counter overflows The overflow period can be set from from 1 to 256 times 8192 or 32 w from approximately 4 ms to 1000...

Page 351: ...tus Register W TCSRW Bit Initial value Read Write 7 B6WI 1 R 6 TCWE 0 R W 5 B4WI 1 R 4 TCSRWE 0 R W 3 B2WI 1 R 0 WRST 0 R W 2 WDON 0 R W 1 B0WI 1 R Note Write is permitted only under certain condition...

Page 352: ...1 Bit 4 is write protected initial value This bit is always read as 1 Data written to this bit is not stored Bit 4 Timer control status register W write enable TCSRWE Bit 4 controls the writing of dat...

Page 353: ...0 Bit 1 Bit 0 write inhibit B0WI Bit 1 controls the writing of data to bit 0 in TCSRW Bit 1 B0WI Description 0 Bit 0 is write enabled 1 Bit 0 is write protected initial value This bit is always read a...

Page 354: ...t performs module standby mode control for peripheral modules Only the bit relating to the watchdog timer is described here For details of the other bits see the sections on the relevant modules Bit 2...

Page 355: ...chdog timer has an 8 bit counter TCW that is incremented by clock input 8192 or w 32 The input clock is selected by bit WDCKS in port mode register 3 PMR3 8192 is selected when WDCKS is cleared to 0 a...

Page 356: ...H F8 TCW overflow Start H F8 written in TCW H F8 written in TCW Reset Internal reset signal 512 OSC clock cycles H FF H 00 TCW count value Example 2 MHz and the desired overflow period is 30 ms The v...

Page 357: ...ation states Table 9 18 Watchdog Timer Operation States Operation Mode Reset Active Sleep Watch Subactive Subsleep Standby Module Standby TCW Reset Functions Functions Halted Functions Halted Halted H...

Page 358: ...count external events input asynchronously without regard to the operation of base clocks and SUB The counter has a 16 bit configuration enabling it to count up to 65536 216 events Can also be used as...

Page 359: ...hronous event input H Asynchronous event input L Event counter overflow interrupt request flag Legend ECCSR ECH ECL AEVH AEVL IRREC Figure 9 19 Block Diagram of Asynchronous Event Counter 3 Pin Config...

Page 360: ...ECH R H 00 H FF96 Event counter L ECL R H 00 H FF97 Clock stop register 2 CKSTP2 R W H FF H FFFB 9 7 2 Register Descriptions 1 Event Counter Control Status Register ECCSR OVH CUEL CRCH CRCL OVL CH2 CU...

Page 361: ...owed Clearing condition After reading OVH 1 cleared by writing 0 to OVH initial value 1 ECH has overflowed Setting condition Set when ECH overflows from H FF to H 00 Bit 6 Counter overflow flag L OVL...

Page 362: ...ich are incremented each time an event clock is input to the AEVH or AEVL pin respectively as asynchronous event input Bit 4 CH2 Description 0 ECH and ECL are used together as a single channel 16 bit...

Page 363: ...Bit 1 Counter reset control H CRCH Bit 1 controls resetting of ECH When this bit is cleared to 0 ECH is reset When 1 is written to this bit the counter reset is cleared and the ECH count up function i...

Page 364: ...8 bit read only up counter that operates either as an independent 8 bit event counter or as the lower 8 bit up counter of a 16 bit event counter configured in combination with ECH The event clock from...

Page 365: ...ECL are used as a 16 bit event counter Start End Clear CH2 to 0 Clear CUEH CUEL CRCH and CRCL to 0 Clear OVH and OVL to 0 Set CUEH CUEL CRCH and CRCL to 1 Figure 9 20 Example of Software Processing wh...

Page 366: ...Event Counters ECH and ECL can be used as 8 bit event counters by carrying out the software processing shown in the example in figure 9 21 The 8 bit event counter operating clock source is asynchrono...

Page 367: ...ncrements during the read operation Therefore if the counter is being used in the 8 bit mode clear bits CUEH and CUEL in ECCSR to 0 before reading ECH or ECL If the counter is being used in the 16 bit...

Page 368: ...5 V 16 MHz H8 38447 Group VCC 4 5 to 5 5 V 16 MHz VCC 2 7 to 5 5 V 10 MHz 8 bit mode Active medium speed sleep medium speed 16 2 fOSC 32 fOSC 64 1 2 fOSC fOSC 1 MHz to 16 MHz 128 1 4 fOSC 8 bit mode...

Page 369: ...or 16 bits Continuous clock output function Choice of 8 internal clocks 1024 to 4 W 4 or external clock Open drain output option Interrupt generated on completion of transfer SCI31 SCI32 Synchronous s...

Page 370: ...s mode It is also provided with a communication function called a Synchronized Serial Bus SSB that enables a number of ICs to be controlled 1 Features Features of SCI1 are listed below Choice of 8 bit...

Page 371: ...SCI1 W 4 SCK1 SI1 SO1 PSS Transmit receive control circuit SCR1 SCSR1 Transfer bit counter SDRU SDRL IRRS1 Transfer bit counter Legend SCR1 Serial control register 1 SCSR1 Serial control status regis...

Page 372: ...lue Address Serial control register 1 SCR1 R W H 00 H FFA0 Serial control status register 1 SCSR1 R W H 9C H FFA1 Serial data register U SDRU R W Undefined H FFA2 Serial data register L SDRL R W Undef...

Page 373: ...e 1 1 1 Reserved 2 Notes 1 Use pins SI1 and SO1 as ports 2 Do not set bits SNC1 and SNC0 to 11 Bit 5 TAIL MARK control MRKON Bit 5 controls tail mark output after transfer of 8 bit or 16 bit data Bit...

Page 374: ...ed to 0 bits 2 to 0 selects the prescaler division ratio and the serial clock cycle Bit 2 Bit 1 Bit 0 Serial Clock Cycle CKS2 CKS1 CKS0 Prescaler Division Ratio 2 5 MHz 0 0 0 1024 initial value 409 6...

Page 375: ...ause incorrect operation so this register should not be manipulated during transmission Note The SOL bit setting is also invalid in SSB mode Bit 6 SOL Description 0 Read SO1 pin output level is low in...

Page 376: ...ing for a start bit and is cleared to 0 when transfer ends Bit 0 STF Description 0 Read Transfer operation stopped initial value Write Invalid 1 Read Transfer operation in progress Write Starts transf...

Page 377: ...ransfer the data written into SDRL is output from the SO1 pin in LSB first order In the replacement process data is input LSB first from the SI1 pin and the data is shifted in the MSB LSB direction Th...

Page 378: ...l clock can be selected from 8 internal clocks or an external clock When an internal clock is selected the SCK1 pin functions as the clock output pin When continuous clock output mode is set SNC1 SNC0...

Page 379: ...taneously with transmit data output When transmission ends the serial clock is not output until the start flag is next set to 1 During this interval the SO1 pin continuously outputs the last bit of th...

Page 380: ...Write the transfer data to SDRL SDRU 8 bit transfer mode SDRL 16 bit transfer mode Upper byte to SDRU lower byte to SDRL 4 When STF is set to 1 in SCSR1 SCI1 starts operating and transmit data is outp...

Page 381: ...B SCL SDA SCL SDA IC C SCK1 SO1 Figure 10 3 Example of SSB Connections 1 Clock The serial clock can be selected from 8 internal clocks or an external clock but since the H8 3847 Group chip provides th...

Page 382: ...NC1 0 SNC0 1 MRKON 1 3 Tail Mark There are two tail marks HOLD TAIL and LATCH TAIL The output waveforms of HOLD TAIL and LATCH TAIL are shown in figure 10 5 Time t in figure 10 5 is determined by the...

Page 383: ...R1 to select SSB mode 4 Write the transfer data to SDRL SDRU Set the tail mark with LTCH in SCR1 8 bit transfer mode SDRL 16 bit transfer mode Upper byte to SDRU lower byte to SDRL 5 When STF is set t...

Page 384: ...pin and an external clock is selected as the clock source the external clock must not be input before transfer operation is started by setting STF to 1 in SCSR1 2 In subactive or subsleep mode SCI1 ca...

Page 385: ...e of asynchronous or synchronous mode for serial data communication Asynchronous mode Serial data communication is performed asynchronously with synchronization provided character by character In this...

Page 386: ...Full duplex communication Separate transmission and reception units are provided enabling transmission and reception to be carried out simultaneously The transmission and reception units are both dou...

Page 387: ...circuit Internal data bus Legend RSR RDR TSR TDR SMR SCR3 SSR BRR BRC SPCR Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial cont...

Page 388: ...guration Table 10 5 shows the SCI3 register configuration Table 10 5 Registers Name Abbr R W Initial Value Address Serial mode register SMR R W H 00 H FFA8 FF98 Bit rate register BRR R W H FF H FFA9 F...

Page 389: ...ically RSR cannot be read or written directly by the CPU 2 Receive Data Register RDR Bit Initial value Read Write 7 RDR7 0 R 6 RDR6 0 R 5 RDR5 0 R 4 RDR4 0 R 3 RDR3 0 R 0 RDR0 0 R 2 RDR2 0 R 1 RDR1 0...

Page 390: ...performed if no data has been written to TDR if bit TDRE is set to 1 in the serial status register SSR TSR cannot be read or written directly by the CPU 4 Transmit Data Register TDR Bit Initial value...

Page 391: ...ule standby mode Bit 7 Communication mode COM Bit 7 selects whether SCI3 operates in asynchronous mode or synchronous mode Bit 7 COM Description 0 Asynchronous mode initial value 1 Synchronous mode Bi...

Page 392: ...even or odd parity is to be used for parity addition and checking The PM bit setting is only valid in asynchronous mode when bit PE is set to 1 enabling parity bit addition and checking The PM bit se...

Page 393: ...eived stop bits is checked irrespective of the STOP bit setting If the second stop bit is 1 it is treated as a stop bit but if 0 it is treated as the start bit of the next transmit character Bit 2 Mul...

Page 394: ...ium and high speed or sleep medium and high speed mode 2 W clock is selected in subactive or subsleep mode SCI3 can be used only when the W 2 is selected as the CPU clock in subactive or subsleep mode...

Page 395: ...ty interrupt request TXI enabled Bit 6 Receive interrupt enable RIE Bit 6 selects enabling or disabling of the receive data full interrupt request RXI and the receive error interrupt request ERI when...

Page 396: ...ettings and setting of bit SPC31 or SPC32 in SPCR to decide the transmission format before setting bit TE to 1 Bit 4 Receive enable RE Bit 4 selects enabling or disabling of the start of receive opera...

Page 397: ...e multiprocessor bit set to 1 is received bit MPBR in SSR is set to 1 bit MPIE is automatically cleared to 0 and RXI and ERI requests when bits TIE and RIE in serial control register 3 SCR3 are set to...

Page 398: ...served Synchronous Reserved Notes 1 Initial value 2 A clock with the same frequency as the bit rate is output 3 Input a clock with a frequency 16 times the bit rate 7 Serial Status Register SSR Bit In...

Page 399: ...d to 0 When data is transferred from TDR to TSR initial value Bit 6 Receive data register full RDRF Bit 6 indicates that received data is stored in RDR Bit 6 RDRF Description 0 There is no receive dat...

Page 400: ...nsmission cannot be continued either Bit 4 Framing error FER Bit 4 indicates that a framing error has occurred during reception in asynchronous mode Bit 4 FER Description 0 Reception in progress or co...

Page 401: ...ed to 0 bit PER is not affected and retains its previous state 2 Receive data in which it a parity error has occurred is still transferred to RDR but bit RDRF is not set Reception cannot be continued...

Page 402: ...es the multiprocessor bit added to transmit data when transmitting in asynchronous mode The bit MPBT setting is invalid when synchronous mode is selected when the multiprocessor communication function...

Page 403: ...ous Mode 1 OSC 32 8 kHz 38 4 kHz 2 MHz 2 4576 MHz 4 MHz Bit Rate bit s n N Error n N Error n N Error n N Error n N Error 110 Cannot be used 2 21 0 83 150 as error exceeds 0 3 0 2 12 0 16 3 3 0 2 25 0...

Page 404: ...16 0 207 0 16 2400 0 64 0 16 0 103 0 16 4800 0 51 0 16 9600 0 25 0 16 19200 0 12 0 16 31250 0 4 0 0 7 0 38400 Notes 1 The setting should be made so that the error is not more than 1 2 The value set in...

Page 405: ...ion rounded to two decimal places Error B rate obtained from n N OSC R bit rate in left hand column in table 10 6 R bit rate in left hand column in table 10 6 100 Table 10 8 shows the maximum bit rate...

Page 406: ...ples of BRR Settings for Various Bit Rates Synchronous Mode 1 OSC 38 4 kHz 2 MHz 4 MHz Bit Rate bit s n N Error n N Error n N Error 200 0 23 0 250 2 124 0 300 2 0 0 500 1k 0 249 0 2 5k 0 99 0 0 199 0...

Page 407: ...Various Bit Rates Synchronous Mode 2 OSC 10 MHz 16 MHz Bit Rate bit s n N Error n N Error 200 250 3 124 0 300 500 2 249 0 1k 2 124 0 2 5k 2 49 0 5k 0 249 0 2 24 0 10k 0 124 0 0 199 0 25k 0 49 0 0 79 0...

Page 408: ...te generator input clock number n 0 2 or 3 The relation between n and the clock is shown in table 10 10 Table 10 10 Relation between n and Clock SMR Setting n Clock CKS1 CKS0 0 0 0 0 W 2 1 W 2 0 1 2 1...

Page 409: ...r SCI31 S31CKSTP Description 0 SCI3 1 is set to module standby mode 1 SCI3 1 module standby mode is cleared initial value Note Setting to module standby mode resets all the registers in SCI31 Bit 5 SC...

Page 410: ...Functions as TXD32 output pin Note Set the TE bit in SCR3 after setting this bit to 1 Bit 4 P35 TXD31 pin function switch SPC31 This bit selects whether pin P35 TXD31 is used as P35 or as TXD31 Bit 4...

Page 411: ...alue 1 RXD32 input data is inverted Bit 1 TXD31 pin output data inversion switch Bit 1 specifies whether or not TXD31 pin output data is to be inverted Bit 1 SCINV1 Description 0 TXD31 output data is...

Page 412: ...combination of these parameters determines the data transfer format and the character length Framing error FER parity error PER overrun error OER and break detection during reception Choice of intern...

Page 413: ...it Parity Bit Stop Bit Length 0 0 0 0 0 Asynchronous 8 bit data No No 1 bit 0 0 0 0 1 mode 2 bits 0 0 0 1 0 Yes 1 bit 0 0 0 1 1 2 bits 0 1 0 0 0 7 bit data No 1 bit 0 1 0 0 1 2 bits 0 1 0 1 0 Yes 1 bi...

Page 414: ...t Receive Clock COM CKE1 CKE0 Mode Clock Source SCK3X Pin Function 0 0 0 Asynchronous Internal I O port SCK3X pin not used 0 0 1 mode Outputs clock with same frequency as bit rate 0 1 0 External Outpu...

Page 415: ...rformed by repeating the above operations until reception of the next RSR data is completed TXI TDRE TIE When TSR is found to be empty on completion of the previous transmission and the transmit data...

Page 416: ...D3x pin Figure 10 7 a RDRF Setting and RXI Interrupt TDR next transmit data TSR transmission in progress TDRE 0 TXD3x pin TDR TSR transmission completed transfer TDRE 1 TXI request when TIE 1 TXD3x pi...

Page 417: ...bit s 5 7 or 8 bits One transfer data unit character or frame 1 bit or none 1 or 2 bits Mark state 1 MSB LSB Figure 10 8 Data Format in Asynchronous Communication In asynchronous communication the co...

Page 418: ...4 5 8 bit data Serial Data Transfer Format and Frame Length SMR STOP S 6 7 8 9 10 11 12 8 bit data S 7 bit data STOP STOP S STOP 7 bit data S STOP STOP 5 bit data S STOP 5 bit data S STOP STOP 8 bit...

Page 419: ...f transmit receive data as shown in figure 10 9 1 character 1 frame 0 D0 D1 D2 D3 D4 D5 D6 D7 0 1 1 1 Clock Serial data Figure 10 9 Phase Relationship between Output Clock and Transfer Data Asynchrono...

Page 420: ...e clock is output immediately after setting bits CKE1 and CKE0 If clock output is selected for reception in synchronous mode the clock is output immediately after bits CKE1 CKE0 and RE are set to 1 Se...

Page 421: ...output Read the serial status register SSR and check that bit TDRE is set to 1 then write transmit data to the transmit data register TDR When data is written to TDR bit TDRE is cleared to 0 automati...

Page 422: ...nsfers data from TDR to TSR and when the stop bit has been sent starts transmission of the next frame If bit TDRE is set to 1 bit TEND in SSR bit is set to 1the mark state in which 1s are transmitted...

Page 423: ...reception No No Yes Receive error processing A Read bits OER PER and FER in the serial status register SSR to determine if there is an error If a receive error has occurred execute receive error proce...

Page 424: ...raming error processing A Parity error processing If a receive error has occurred read bits OER PER and FER in SSR to identify the error and after carrying out the necessary error processing ensure th...

Page 425: ...checks bit RDRF is set to 1 and the receive data is stored in RDR If bit RIE is set to 1 in SCR3 an RXI interrupt is requested If the error checks identify a receive error bit OER PER or FER is set to...

Page 426: ...g RXI request 0 start bit detected ERI request in response to framing error Figure 10 14 Example of Operation when Receiving in Asynchronous Mode 8 bit data parity 1 stop bit 3 Operation in Synchronou...

Page 427: ...transfer data character begins with the LSB and ends with the MSB After output of the MSB the communication line retains the MSB state When receiving in synchronous mode SCI3 latches receive data at...

Page 428: ...tion Data transfer on SCI3 first of all requires that SCI3 be initialized as described in SCI initialization under 10 3 3 2 c Data transfer operations and shown in figure 10 10 Transmitting Figure 10...

Page 429: ...is set to 1 then write transmit data to the transmit data register TDR When data is written to TDR bit TDRE is cleared to 0 automatically the clock is output and data transmission is started When clo...

Page 430: ...bit TDRE is cleared to 0 SCI3 transfers data from TDR to TSR and starts transmission of the next frame If bit TDRE is set to 1 SCI3 sets bit TEND to 1 in SSR and after sending the MSB bit 7 retains t...

Page 431: ...processing Read bit OER in the serial status register SSR to determine if there is an error If an overrun error has occurred execute overrun error processing Read SSR and check that bit RDRF is set t...

Page 432: ...check identifies an overrun error bit OER is set to 1 Bit RDRF remains set to 1 If bit RIE is set to 1 in SCR3 an ERI interrupt is requested See table 10 15 for the conditions for detecting a receive...

Page 433: ...ta transmission reception finish reading of bit RDRF and RDR before receiving the MSB bit 7 of the current frame Before receiving the MSB bit 7 of the current frame also read TDRE 1 to confirm that a...

Page 434: ...a is sent to the specified receiver These two cycles are differentiated by means of the multiprocessor bit 1 indicating an ID transmission cycle and 0 a data transmission cycle The sender first sends...

Page 435: ...1 Example of Inter Processor Communication Using Multiprocessor Format Sending data H AA to receiver A There is a choice of four data transfer formats If a multiprocessor format is specified the parit...

Page 436: ...and check that bit TDRE is set to 1 then set bit MPBT in SSR to 0 or 1 and write transmit data to the transmit data register TDR When data is written to TDR bit TDRE is cleared to 0 automatically Whe...

Page 437: ...t TDRE is set to 1 bit TEND in SSR bit is set to 1 the mark state in which 1s are transmitted is established after the stop bit has been sent If bit TEIE in SCR3 is set to 1 at this time a TEI request...

Page 438: ...r has occurred execute receive error processing Read SSR and check that bit RDRF is set to 1 If it is read the receive data in RDR and compare it with this receiver s own ID If the ID is not this rece...

Page 439: ...ng End of receive error processing Clear bits OER and FER to 0 in SSR Yes OER 1 Yes Yes FER 1 Break No No No Overrun error processing Framing error processing A Figure 10 24 Example of Multiprocessor...

Page 440: ...receiver s ID bit MPIE is set to 1 again 1 frame Start bit Start bit Receive data ID2 Receive data Data2 MPB MPB Stop bit Stop bit Mark state idle state 1 frame 0 1 D0 D1 D7 1 1 1 1 0 a When data doe...

Page 441: ...These two interrupts are generated during transmission The initial value of bit TDRE in SSR is 1 Therefore if the transmit data empty interrupt request TXI is enabled by setting bit TIE to 1 in SCR3 b...

Page 442: ...then write the transmit data to TDR once only not two or more times 2 Operation when a Number of Receive Errors Occur Simultaneously If a number of receive errors are detected simultaneously the stat...

Page 443: ...E is cleared to 0 at this time the TXD3X pin functions as an I O port and 1 is output To detect a break clear bit TE to 0 after setting PCR 1 and PDR 0 When bit TE is cleared to 0 the transmission uni...

Page 444: ...mode can be expressed as shown in equation 1 M 0 5 1 2N D 0 5 N L 0 5 F 100 Equation 1 where M Receive margin N Ratio of bit rate to clock N 16 D Clock duty D 0 5 to 1 0 L Frame length L 9 to 12 F Abs...

Page 445: ...s is illustrated in figure 10 27 Communication line RDRF RDR Frame 1 Frame 2 Frame 3 Data 1 Data 1 RDR read RDR read Data 1 is read at point A Data 2 Data 3 Data 2 A Data 2 is read at point B B Figure...

Page 446: ...command In this case use the COM bit in SMR set at 1 This means it cannot be used as an I O port Also to avoid intermediate potential from being applied to the SCK3X pin pull up the line connected to...

Page 447: ...are as follows Choice of two conversion periods Any of the following four conversion periods can be chosen 131 072 with a minimum modulation width of 8 PWCR1 1 PWCR0 1 65 536 with a minimum modulatio...

Page 448: ...PWDRU PWCR PWM waveform generator 2 4 8 16 Legend PWDRL PWDRU PWCR PWM data register L PWM data register U PWM control register PWM Figure 11 1 Block Diagram of the 14 bit PWM 11 1 3 Pin Configuration...

Page 449: ...FFD0 PWM data register U PWDRU W H C0 H FFD1 PWM data register L PWDRL W H 00 H FFD2 Clock stop register 2 CKSTPR2 R W H FF H FFFB 11 2 Register Descriptions 11 2 1 PWM Control Register PWCR Bit Init...

Page 450: ...CR0 Description 0 0 The input clock is 2 t 2 The conversion period is 16 384 with a minimum modulation width of 1 initial value 0 1 The input clock is 4 t 4 The conversion period is 32 768 with a mini...

Page 451: ...t write only register with the upper 6 bits assigned to PWDRU and the lower 8 bits to PWDRL The value written to PWDRU and PWDRL gives the total high level width of one PWM waveform cycle When 14 bit...

Page 452: ...bit read write register that performs module standby mode control for peripheral modules Only the bit relating to the PWM is described here For details of the other bits see the sections on the relev...

Page 453: ...ration in synchronization with internal signals One conversion period consists of 64 pulses as shown in figure 11 2 The total of the high level pulse widths during this period TH corresponds to the da...

Page 454: ...ure 11 2 PWM Output Waveform 11 3 2 PWM Operation Modes PWM operation modes are shown in table 11 3 Table 11 3 PWM Operation Modes Operation Mode Reset Active Sleep Watch Subactive Subsleep Standby Mo...

Page 455: ...up to 12 channels of analog input 12 1 1 Features The A D converter has the following features 10 bit resolution 12 input channels Conversion time approx 12 4 s per channel at 5 MHz operation Built in...

Page 456: ...nal data bus AMR ADSR ADRRH ADRRL Control logic Com parator AN AN AN AN AN AN AN AN AN AN AN AN ADTRG AV AV CC SS Multiplexer Reference voltage IRRAD AVCC AVSS 0 1 2 3 4 5 6 7 8 9 10 11 Legend AMR ADS...

Page 457: ...log input 5 AN5 Input Analog input channel 5 Analog input 6 AN6 Input Analog input channel 6 Analog input 7 AN7 Input Analog input channel 7 Analog input 8 AN8 Input Analog input channel 8 Analog inpu...

Page 458: ...conversion The upper 8 bits of the data are held in ADRRH and the lower 2 bits in ADRRL ADRRH and ADRRL can be read by the CPU at any time but the ADRRH and ADRRL values during A D conversion are not...

Page 459: ...trical Characteristics Bit 6 External trigger select TRGE Bit 6 enables or disables the start of A D conversion by external trigger input Bit 6 TRGE Description 0 Disables start of A D conversion by e...

Page 460: ...0 0 AN4 1 0 0 1 AN5 1 0 1 0 AN6 1 0 1 1 AN7 1 1 0 0 AN8 1 1 0 1 AN9 1 1 1 0 AN10 1 1 1 1 AN11 Don t care 12 2 3 A D Start Register ADSR Bit Initial value Read Write 7 ADSF 0 R W 6 1 5 1 4 1 3 1 0 1 2...

Page 461: ...ister 1 CKSTPR1 S1CKSTP TFCKSTP TCCKSTP TACKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W Bit Initial value Read Write CKSTPR1 is an 8 bit read...

Page 462: ...r 2 IENR2 is set to 1 If the conversion time or input channel needs to be changed in the A D mode register AMR during A D conversion bit ADSF should first be cleared to 0 stopping the conversion opera...

Page 463: ...d interrupts can be enabled or disabled by means of bit IENAD in interrupt enable register 2 IENR2 For further details see section 3 3 Interrupts 12 5 Typical Use An example of how the A D converter c...

Page 464: ...4 and 12 5 show flow charts of procedures for using the A D converter Idle A D conversion 1 Idle A D conversion 2 Idle Interrupt IRRAD IENAD ADSF Channel 1 AN1 operation state ADRRH ADRRL Set Set Set...

Page 465: ...0600 Start Set A D conversion speed and input channel Perform A D conversion End Yes No Disable A D conversion end interrupt Start A D conversion ADSF 0 No Yes Read ADSR Read ADRRH ADRRL data Figure...

Page 466: ...form A D conversion Figure 12 5 Flow Chart of Procedure for Using A D Converter Interrupts Used 12 6 Application Notes 12 6 1 Application Notes Data in ADRRH and ADRRL should be read only when the A D...

Page 467: ...fficient and it may not be possible to guarantee A D conversion precision However a large capacitance provided externally the input load will essentially comprise only the internal input resistance of...

Page 468: ...Section 12 A D Converter Rev 6 00 Aug 04 2006 page 430 of 680 REJ09B0145 0600...

Page 469: ...4 40 seg 64 seg Note The external expansion function for LCD segments is not implemented in the H8 38347 Group and H8 38447 Group LCD RAM capacity 8 bits 32 bytes 256 bits Word access to LCD RAM All...

Page 470: ...bytes Internal data bus 40 bit shift register LCD drive power supply Segment driver Common data latch Common driver M V1 V2 V3 VSS COM1 COM4 SEG40 CL1 SEG39 CL2 SEG38 DO SEG37 M SEG36 SEG1 Legend LPCR...

Page 471: ...isplay data shift clock SEG39 M Output Multiplexed as the LCD alternating signal SEG37 DO Output Multiplexed as the serial display data SEG38 LCD power supply pins V0 V1 V2 V3 Used when a bypass capac...

Page 472: ...ation of DTS1 and DTS0 selects static 1 2 1 3 or 1 4 duty CMX specifies whether or not the same waveform is to be output from multiple pins to increase the common drive power when not all common pins...

Page 473: ...lue 1 CL1 CL2 DO and M pins Note Functions as ports when SGS3 to SGS0 are set at 0000 Bits 3 to 0 Segment driver select 3 to 0 SGS3 to SGS0 Bits 3 to 0 select the segment drivers to be used The SGX 0...

Page 474: ...used to turn the LCD drive power supply off when LCD display is not required in a power down mode or when an external power supply is used When the ACT bit is cleared to 0 or in standby mode the LCD d...

Page 475: ...therefore display operations are not performed if one of the clocks from 2 to 256 is selected If LCD display is required in these modes w w 2 or w 4 must be selected as the operating clock Bit 3 Bit...

Page 476: ...the charge discharge pulses which control disconnection of the power supply split resistance from the power supply circuit LCR2 is initialized to H 60 upon reset Bit 7 A waveform B waveform switching...

Page 477: ...elect the duty cycle while the power supply split resistance is connected to the power supply circuit When a 0 duty cycle is selected the power supply split resistance is permanently disconnected from...

Page 478: ...ule standby mode control for peripheral modules Only the bit relating to the LCD controller driver is described here For details of the other bits see the sections on the relevant modules Bit 0 LCD co...

Page 479: ...istance is large it may not be suitable for driving a large panel If the display lacks sharpness when using a large panel refer to section 13 3 6 Boosting the LCD Drive Power Supply When static or 1 2...

Page 480: ...y connect the external power supply to the V1 pin and short the V0 pin to VCC externally as shown in figure 13 4 b VCC V1 V2 V3 VSS V0 a Using on chip power supply circuit VCC V1 V2 V3 VSS V0 b Using...

Page 481: ...used can be selected with bits SGS3 to SGS0 c Frame frequency selection The frame frequency can be selected by setting bits CKS3 to CKS0 The frame frequency should be selected in accordance with the L...

Page 482: ...nally expanded are shown in figures 13 9 to 13 12 After setting the registers required for display data is written to the part corresponding to the duty using the same kind of instruction as for ordin...

Page 483: ...EJ09B0145 0600 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SEG2 SEG2 SEG2 SEG1 SEG1 SEG1 H F740 H F753 SEG40 SEG40 SEG40 SEG39 SEG39 SEG39 COM3 COM2 COM1 COM3 COM2 COM1 Space not used for display...

Page 484: ...Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SEG4 SEG4 SEG3 SEG3 SEG2 SEG2 SEG1 SEG1 SEG40 H F740 H F74A H F753 SEG40 SEG39 SEG39 SEG38 SEG38 SEG37 SEG37 COM2 COM1 COM2 COM1 COM2 COM1 COM2 COM1 Display space...

Page 485: ...it 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG40 H F740 H F745 H F753 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1 Space not used f...

Page 486: ...Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SEG2 SEG2 SEG2 SEG2 SEG1 SEG1 SEG1 SEG1 SEG64 H F740 H F75F SEG64 SEG64 SEG64 SEG63 SEG63 SEG63 SEG63 COM4 COM3 COM2 COM1 COM4 COM3 COM2 COM1 Expansion driver displ...

Page 487: ...6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SEG2 SEG2 SEG2 SEG1 SEG1 SEG1 H F740 H F75F SEG64 SEG64 SEG64 SEG63 SEG63 SEG63 COM3 COM2 COM1 COM3 COM2 COM1 Space not used for display Expansion driver display...

Page 488: ...Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SEG4 SEG4 SEG3 SEG3 SEG2 SEG2 SEG1 SEG1 SEG128 H F740 H F75F SEG128 SEG127 SEG127 SEG126 SEG126 SEG125 SEG125 COM2 COM1 COM2 COM1 COM2 COM1 COM2 COM1 Expansion driver di...

Page 489: ...5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG256 H F740 H F75F SEG255 SEG254 SEG253 SEG252 SEG251 SEG250 SEG249 COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1 Expansion driver d...

Page 490: ...ply unit The voltage output to the V0 pin is VCC When this voltage is used directly as the LCD drive power supply the V0 and V1 pins should be shorted Also connecting a variable resistance R between t...

Page 491: ...example with 1 3 bias drive the charge for V2 is 2 3 that of V1 and that for V3 is 1 3 that of V1 4 Power is supplied to the LCD panel by means of the charges accumulated in these capacitors 5 The ca...

Page 492: ...g discharging periods must be determined experimentally in accordance with the current dissipation requirements of the LCD panel An optimum current value can be selected in contrast to the case in whi...

Page 493: ...2 V3 VSS V1 V2 V3 VSS a Waveform with 1 4 duty 1 frame M Data COM1 COM2 COM3 SEGn V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS 1 frame M Data COM1 COM2 SEGn V1 V2 V3 VSS V1 V2 V3 VSS 1 frame M...

Page 494: ...ame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame b Waveform with 1 3 duty M Data COM3 SEGn COM1 V1 V2 V3 VSS COM2 V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS a Waveform with 1 4 duty M Data COM1...

Page 495: ...pplied and display will halt Since there is a possibility that a direct current will be applied to the LCD panel in this case it is essential to ensure that w w 2 or w 4 is selected In active medium s...

Page 496: ...supply capacity may be insufficient In this case the power supply impedance must be reduced This can be done by connecting bypass capacitors of around 0 1 to 0 3 F to pins V1 to V3 as shown in figure...

Page 497: ...6100 The output level is determined by a combination of the data and the M pin output but these combinations differ from those in the HD66100 Table 13 3 shows the output levels of the LCD drive power...

Page 498: ...V1 V2 V3 VSS SEG40 CL1 SEG39 CL2 SEG38 DO SEG37 M This LSI VCC V0 V1 V2 V3 VSS SEG40 CL1 SEG39 CL2 SEG38 DO SEG37 M VCC V1 V4 V3 V2 GND VEE SHL CL1 CL2 DI M This LSI HD66100 VCC V1 V4 V3 V2 GND VEE SH...

Page 499: ...r supply step down circuit 14 2 When Using Internal Power Supply Step Down Circuit Connect the external power supply to the VCC pin and connect a capacitance of approximately 0 1 F in the case of the...

Page 500: ...tep Down Circuit is Not Used 14 4 H8 3847S Group The H8 3847S Group has two VCC pins which should be interconnected externally 14 5 Notes on Switching from the H8 3847R to the H8 38347 or H8 38447 Exa...

Page 501: ...ming voltage VPP 0 3 to 13 0 V Input voltage Ports other than Ports B and C Vin 0 3 to VCC 0 3 V Ports B and C AVin 0 3 to AVCC 0 3 V Operating temperature Topr 20 to 75 2 C Storage temperature Tstg 5...

Page 502: ...oscillator frequency range 16 0 10 0 4 0 2 0 1 8 2 7 4 5 5 5 VCC V f osc MHz 38 4 1 8 3 6 5 5 VCC V f W kHz Active high speed mode Sleep high speed mode Internal power supply step down circuit not us...

Page 503: ...r supply step down circuit used Active medium speed mode except A D converter Sleep medium speed mode except A D converter Internal power supply step down circuit used Subactive mode Subsleep mode exc...

Page 504: ...2 7 4 5 5 5 AVCC V kHz 625 500 1 8 2 7 4 5 5 5 AVCC V kHz Active medium speed mode Sleep medium speed mode Internal power supply step down circuit not used 5 0 1 0 0 5 5 5 AVCC V MHz Active high speed...

Page 505: ...Q4 AEVL AEVH TMIC TMIF 0 8 VCC VCC 0 3 V VCC 4 0 V to 5 5 V Input high voltage TMIG SCK1 SCK31 SCK32 ADTRG 0 9 VCC VCC 0 3 Except the above SI1 RXD31 RXD32 UD 0 7 VCC VCC 0 3 V VCC 4 0 V to 5 5 V 0 8...

Page 506: ...0 1 VCC V VCC 1 8 V to 5 5 V P10 to P17 P20 to P27 P30 to P37 P40 to P43 P50 to P57 P60 to P67 0 3 0 3 VCC V VCC 4 0 V to 5 5 V P70 to P77 P80 to P87 P90 to P97 PA0 to PA3 PB0 to PB7 PC0 to PC3 0 3 0...

Page 507: ...7 PC0 to PC3 1 0 VIN 0 5 V to AVCC 0 5 V Ip P10 to P17 P30 to P37 50 0 300 0 A VCC 5 V VIN 0 V Pull up MOS current P50 to P57 P60 to P67 35 0 VCC 2 7 V VIN 0 V Refer ence value CIN All input pins exce...

Page 508: ...V LCD on 32 kHz crystal oscillator SUB W 2 3 5 6 Watch mode current dissi pation IWATCH VCC 2 8 6 0 A VCC 2 7 V 32 kHz crystal oscillator LCD not used 3 5 6 Stand by mode current dissi pation ISTBY V...

Page 509: ...Pins LCD Power Supply Oscillator Pins Active high speed mode VCC Only CPU Operates VCC Halted System clock oscillator Crystal Active medium speed mode Subclock oscillator Pin X1 GND Sleep mode VCC On...

Page 510: ...5 5 V 2 2 10 VCC 2 7 V to 5 5 V System clock oscillation frequency 2 4 VCC 1 8 V to 5 5 V OSC clock OSC cycle time tOSC OSC1 OSC2 62 5 500 1000 ns VCC 4 5 V to 5 5 V Figure 15 1 2 3 100 500 1000 VCC 2...

Page 511: ...CC 4 5 V to 5 5 V Figure 15 1 2 40 VCC 2 7 V to 5 5 V Figure 15 1 100 VCC 1 8 V to 5 5 V X1 15 26 or 13 02 s External clock rise time tCPr OSC1 6 ns VCC 4 5 V to 5 5 V Figure 15 1 2 10 VCC 2 7 V to 5...

Page 512: ...DTRG TMIC TMIF TMIG AEVL AEVH 2 tcyc tsubcyc Figure 15 3 UD pin minimum modulation width tUDH tUDL UD 4 tcyc tsubcyc Figure 15 4 Notes 1 Selected with SA1 and SA0 of system clock control register 2 SY...

Page 513: ...60 0 ns VCC 4 0 V to 5 5 V Figure 15 5 1 time 80 0 ns Except the above Figure 15 5 Input clock fall tSCKf SCK1 60 0 ns VCC 4 0 V to 5 5 V Figure 15 5 1 time 80 0 ns Except the above Figure 15 5 Seria...

Page 514: ...6 cycle Synchronous 6 tsubcyc Input clock pulse width tSCKW 0 4 0 6 tScyc Figure 15 6 Transmit data delay time tTXD 1 tcyc or VCC 4 0 V to 5 5 V Figure 15 7 synchronous 1 tsubcyc Except the above Rec...

Page 515: ...impedance RAIN 10 0 k Resolution data length 10 bit Nonlinearity error 2 5 LSB AVCC 2 7 V to 5 5 V VCC 2 7 V to 5 5 V 4 5 5 AVCC 2 0 V to 5 5 V VCC 2 0 V to 5 5 V 7 5 Except the above 5 Quantization...

Page 516: ...r drop voltage VDS SEG1 to SEG40 0 6 V ID 2 A V1 2 7 V to 5 5 V 1 Common driver drop voltage VDC COM1 to COM4 0 3 V ID 2 A V1 2 7 V to 5 5 V 1 LCD power supply split resistance RLCD 0 5 3 0 9 0 M Betw...

Page 517: ...Conditions Figure Clock high width tCWH CL1 CL2 800 0 ns 1 Figure 15 8 Clock low width tCWL CL2 800 0 ns 1 Figure 15 8 Clock setup time tCSU CL1 CL2 500 0 ns 1 Figure 15 8 Data setup time tSU DO 300 0...

Page 518: ...nalog power supply voltage AVCC 0 3 to 7 0 V Programming voltage VPP 0 3 to 13 0 V Input voltage Ports other than Ports B and C Vin 0 3 to VCC 0 3 V Ports B and C AVin 0 3 to AVCC 0 3 V Operating temp...

Page 519: ...r frequency range 16 0 10 0 4 0 2 0 1 8 2 7 4 5 5 5 VCC V f osc MHz 38 4 1 8 3 6 5 5 VCC V f W kHz Active high speed mode Sleep high speed mode Internal power supply step down circuit not used Note fo...

Page 520: ...r supply step down circuit used Active medium speed mode except A D converter Sleep medium speed mode except A D converter Internal power supply step down circuit used Subactive mode Subsleep mode exc...

Page 521: ...2 7 4 5 5 5 AVCC V kHz 625 500 1 8 2 7 4 5 5 5 AVCC V kHz Active medium speed mode Sleep medium speed mode Internal power supply step down circuit not used 5 0 1 0 0 5 5 5 AVCC V MHz Active high speed...

Page 522: ...to WKP7 IRQ0 to IRQ4 AEVL AEVH TMIC TMIF 0 8 VCC VCC 0 3 V VCC 4 0 V to 5 5 V TMIG SCK1 SCK31 SCK32 ADTRG 0 9 VCC VCC 0 3 Except the above SI1 RXD31 RXD32 UD 0 7 VCC VCC 0 3 V VCC 4 0 V to 5 5 V 0 8...

Page 523: ...0 1 VCC V VCC 1 8 V to 5 5 V P10 to P17 P20 to P27 P30 to P37 P40 to P43 P50 to P57 P60 to P67 0 3 0 3 VCC V VCC 4 0 V to 5 5 V P70 to P77 P80 to P87 P90 to P97 PA0 to PA3 PB0 to PB7 PC0 to PC3 0 3 0...

Page 524: ...7 PC0 to PC3 1 0 VIN 0 5 V to AVCC 0 5 V Ip P10 to P17 P30 to P37 50 0 300 0 A VCC 5 V VIN 0 V Pull up MOS current P50 to P57 P60 to P67 35 0 VCC 2 7 V VIN 0 V Refer ence value CIN All input pins exce...

Page 525: ...V LCD on 32 kHz crystal oscillator SUB W 2 3 4 5 Watch mode current dissi pation IWATCH VCC 2 8 6 0 A VCC 2 7 V 32 kHz crystal oscillator LCD not used 3 4 5 Stand by mode current dissi pation ISTBY V...

Page 526: ...ent Mode RES RES RES RES Pin Internal State Other Pins LCD Power Supply Oscillator Pins Active high speed mode VCC Only CPU Operates VCC Halted System clock oscillator Crystal Active medium speed mode...

Page 527: ...5 5 V 2 2 10 VCC 2 7 V to 5 5 V System clock oscillation frequency 2 4 VCC 1 8 V to 5 5 V OSC clock OSC cycle time tOSC OSC1 OSC2 62 5 500 1000 ns VCC 4 5 V to 5 5 V Figure 15 1 2 3 100 500 1000 VCC...

Page 528: ...CC 4 5 V to 5 5 V Figure 15 1 2 40 VCC 2 7 V to 5 5 V Figure 15 1 100 VCC 1 8 V to 5 5 V X1 15 26 or 13 02 s External clock rise time tCPr OSC1 6 ns VCC 4 5 V to 5 5 V Figure 15 1 2 10 VCC 2 7 V to 5...

Page 529: ...n low width tIL IRQ0 to IRQ4 WKP0 to WKP7 ADTRG TMIC TMIF TMIG AEVL AEVH 2 tcyc tsubcyc Figure 15 3 UD pin minimum modulation width tUDH tUDL UD 4 tcyc tsubcyc Figure 15 4 Notes 1 Selected with SA1 an...

Page 530: ...0 4 tScyc Figure 15 5 Input clock rise tSCKr SCK1 60 0 ns VCC 4 0 V to 5 5 V Figure 15 5 time 80 0 ns Except the above Figure 15 5 Input clock fall tSCKf SCK1 60 0 ns VCC 4 0 V to 5 5 V Figure 15 5 ti...

Page 531: ...chronous tScyc 4 tcyc or Figure 15 6 cycle Synchronous 6 tsubcyc Input clock pulse width tSCKW 0 4 0 6 tScyc Figure 15 6 Transmit data delay time tTXD 1 tcyc or VCC 4 0 V to 5 5 V Figure 15 7 synchron...

Page 532: ...AN0 to AN11 15 0 pF Allowable signal source impedance RAIN 10 0 k Resolution data length 10 bit Nonlinearity error 2 5 LSB AVCC 2 7 V to 5 5 V VCC 2 7 V to 5 5 V 4 5 5 AVCC 2 0 V to 5 5 V VCC 2 0 V to...

Page 533: ...Typ Max Unit Conditions Notes Segment driver drop voltage VDS SEG1 to SEG40 0 6 V ID 2 A V1 2 7 V to 5 5 V 1 Common driver drop voltage VDC COM1 to COM4 0 3 V ID 2 A V1 2 7 V to 5 5 V 1 LCD power supp...

Page 534: ...Test Reference Item Symbol Pins Min Typ Max Unit Conditions Figure Clock high width tCWH CL1 CL2 800 0 ns Figure 15 8 Clock low width tCWL CL2 800 0 ns Figure 15 8 Clock setup time tCSU CL1 CL2 500 0...

Page 535: ...s other than Port B C Vin 0 3 to VCC 0 3 V Port B C AVin 0 3 to AVCC 0 3 V Operating temperature Topr 20 to 75 Regular specifications C 40 to 85 wide range specifications 75 products shipped as chips...

Page 536: ...e The power supply voltage and operating range are indicated by the shaded region in the figures 1 Power supply voltage and oscillator frequency range 10 0 4 0 2 0 1 8 2 7 3 6 VCC V f osc MHz 38 4 1 8...

Page 537: ...CPU Subactive mode Subsleep mode except CPU Watch mode except CPU Figures in parentheses are the minimum operating frequency of a case external clocks are used When using an oscillator the minimum ope...

Page 538: ...0 3 V P10 to P17 P20 to P27 P30 to P37 P40 to P43 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 PA0 to PA3 0 8 VCC VCC 0 3 V PB0 to PB7 PC0 to PC3 0 8 VCC AVCC 0 3 Input low voltage VIL RES W...

Page 539: ...1 X1 P10 to P17 P20 to P27 P30 to P37 P40 to P43 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 PA0 to PA3 1 0 A VIN 0 5 V to VCC 0 5 V PB0 to PB7 PC0 to PC3 1 0 VIN 0 5 V to AVCC 0 5 V Pull u...

Page 540: ...128 0 7 1 6 Active medium speed mode VCC 3 V fOSC 10 MHz OSC 128 ISLEEP VCC 0 2 3 mA VCC 1 8 V fOSC 2 MHz 1 2 0 6 3 VCC 3 V fOSC 4 MHz Sleep mode current dissipa tion 1 4 2 9 VCC 3 V fOSC 10 MHz ISUB...

Page 541: ...ystal oscillator LCD not used 2 8 6 VCC 2 7 V 32 kHz crystal oscillator LCD not used ISTBY VCC 0 3 3 A 32 kHz crystal oscillator not used VCC 1 8 V Ta 25 C 1 2 Stand by mode current dissipa tion 0 5 3...

Page 542: ...Only CPU Operates VCC Halted System clock oscillator Crystal Active medium speed mode Subclock oscillator Pin X1 GND Sleep mode VCC Only timers operate VCC Subactive mode VCC Only CPU Operates VCC Ha...

Page 543: ...SC OSC1 OSC2 100 500 1000 ns VCC 2 7 V to 3 6 V Figure 15 1 2 OSC clock OSC cycle time 250 500 1000 VCC 1 8 V to 3 6 V tcyc 2 128 tOSC System clock cycle time 128 s Subclock oscilla tion frequency fW...

Page 544: ...o 3 6 V X1 15 26 or 13 02 s tCPL OSC1 40 ns VCC 2 7 V to 3 6 V Figure 15 1 External clock low width 100 VCC 1 8 V to 3 6 V X1 15 26 or 13 02 s tCPr OSC1 10 ns VCC 2 7 V to 3 6 V Figure 15 1 External c...

Page 545: ...e Values Reference Item Symbol Pins Min Typ Max Unit Test Condition Figure UD pin minimum modulation width tUDH tUDL UD 4 tcyc tsubcyc Figure 15 4 Notes 1 Selected with SA1 and SA0 of system clock con...

Page 546: ...ycle tScyc SCK1 4 tcyc Figure 15 5 Input clock high width tSCKH SCK1 0 4 tScyc Figure 15 5 Input clock low width tSCKL SCK1 0 4 tScyc Figure 15 5 Input clock rise time tSCKr SCK1 80 0 ns Figure 15 5 I...

Page 547: ...in Typ Max Unit Test Conditions Figure Input clock Asynchronous tScyc 4 tcyc or Figure 15 6 cycle Synchronous 6 tsubcyc Input clock pulse width tSCKW 0 4 0 6 tScyc Figure 15 6 Transmit data delay time...

Page 548: ...AN11 15 0 pF Allowable signal source impedance RAIN 10 0 k Resolution data length 10 bit Nonlinearity error 3 5 LSB AVCC 2 7 V to 3 6 V VCC 2 7 V to 3 6 V 5 5 AVCC 2 0 V to 3 6 V VCC 2 0 V to 3 6 V 7...

Page 549: ...S SEG1 to SEG40 0 6 V ID 2 A V1 2 7 V to 3 6 V 1 Common driver drop voltage VDC COM1 to COM4 0 3 V ID 2 A V1 2 7 V to 3 6 V 1 LCD power supply split resistance RLCD 1 5 3 5 7 M Between V1 and VSS Liqu...

Page 550: ...onditions Figure Clock high width tCWH CL1 CL2 800 0 ns Figure 15 8 Clock low width tCWL CL2 800 0 ns Figure 15 8 Clock setup time tCSU CL1 CL2 500 0 ns Figure 15 8 Data setup time tSU DO 300 0 ns Fig...

Page 551: ...orts B C AVin 0 3 to AVCC 0 3 V Operating temperature Topr 20 to 75 2 regular specifications C 40 to 85 2 wide range temperature specifications 75 3 chip shipment specifications Storage temperature Ts...

Page 552: ...re shown below 1 Power Supply Voltage and Oscillation Frequency Range 5 5 VCC V f W kHz All operating modes 32 768 38 4 2 7 5 5 VCC V f W kHz All operating modes 32 768 38 4 2 7 2 0 16 0 2 7 5 5 VCC V...

Page 553: ...25 2 7 5 5 VCC V kHz Active medium speed mode Sleep medium speed mode except A D converter Notes 1 The figure in parentheses indicates the minimum operating frequency when an external clock is used Wh...

Page 554: ...Range 8 0 0 5 1 0 2 7 5 5 AVCC V MHz Active high speed mode Sleep high speed mode 1000 500 2 7 5 5 AVCC V kHz Active medium speed mode Sleep medium speed mode H8 38347 Group 5 0 0 5 1 0 2 7 5 5 AVCC V...

Page 555: ...ES WKP0 to WKP7 IRQ0 to IRQ4 AEVL AEVH TMIC TMIF TMIG ADTRG SCK1 SCK32 SCK31 VCC 0 9 VCC 0 3 Other than above VCC 0 7 VCC 0 3 V VCC 4 0 V to 5 5 V RXD32 UD RXD31 SI1 VCC 0 8 VCC 0 3 Other than above O...

Page 556: ...RXD32 UD RXD31 SI1 0 3 VCC 0 2 Other than above OSC1 0 3 VCC 0 2 V VCC 4 0 V to 5 5 V 0 3 VCC 0 1 Other than above EXCL 0 3 VCC 0 1 V 0 3 VCC 0 3 V VCC 4 0 V to 5 5 V P10 to P17 P20 to P27 P30 to P37...

Page 557: ...CC 4 0 V to 5 5 V IOL 10 mA 0 6 VCC 4 0 V to 5 5 V IOL 1 6 mA 0 5 IOL 0 4 mA IIL RES P43 OSC1 X1 P10 to P17 P20 to P27 P30 to P37 P40 to P42 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 PA0...

Page 558: ...8 mA Active high speed mode VCC 2 7 V fOSC 2 MHz 1 3 4 Approx max value 1 1 Typ 1 2 2 3 4 Approx max value 1 1 Typ 1 0 Active high speed mode VCC 5 V fOSC 2 MHz 1 3 4 Approx max value 1 1 Typ 1 5 2 3...

Page 559: ...peed mode VCC 2 7 V fOSC 2 MHz OSC 128 1 3 4 Approx max value 1 1 Typ 0 7 2 3 4 Approx max value 1 1 Typ 0 5 Active medium speed mode VCC 5 V fOSC 2 MHz OSC 128 1 3 4 Approx max value 1 1 Typ 1 0 2 3...

Page 560: ...rox max value 1 1 Typ 0 7 VCC 5 V fOSC 2 MHz 1 3 4 Approx max value 1 1 Typ 1 2 2 3 4 Approx max value 1 1 Typ 1 1 VCC 5 V fOSC 4 MHz 1 3 4 Approx max value 1 1 Typ 1 6 2 3 4 Approx max value 1 1 Typ...

Page 561: ...ystal resonator used LCD not used 2 3 4 Reference value Watch mode current consump tion 3 0 6 0 VCC 2 7 V 32 kHz crystal resonator used LCD not used 3 4 ISTBY VCC 0 3 A VCC 2 7 V Ta 25 C 32 kHz crysta...

Page 562: ...0 V to 5 5 V All pins 0 5 Allowable output low current total IOL Output pins except ports 2 and 3 40 0 mA VCC 4 0 V to 5 5 V Ports 2 and 3 80 0 VCC 4 0 V to 5 5 V All pins 20 0 IOH All output pins 2...

Page 563: ...em clock crystal resonator Subclock Pin X1 GND Subactive mode VCC Only CPU operates VCC Stops Subsleep mode VCC Only all on chip timers operate CPU stops VCC Stops Watch mode VCC Only clock time base...

Page 564: ...oscillation frequency fOSC OSC1 OSC2 2 0 10 0 VCC 2 7 to 5 5 V 4 62 5 500 1000 ns Figure 15 1 2 3 62 5 500 1000 VCC 4 5 to 5 5 V OSC clock OSC cycle time tOSC OSC1 OSC2 100 500 1000 VCC 2 7 to 5 5 V...

Page 565: ...idth tCPL OSC1 25 ns Figure 15 1 3 25 VCC 4 5 to 5 5 V 40 VCC 2 7 to 5 5 V Figure 15 1 4 EXCL 15 26 or 13 02 s Figure 15 1 External clock rise time tCPr OSC1 6 ns Figure 15 1 3 6 VCC 4 5 to 5 5 V 10 V...

Page 566: ...is used 3 Also applies to H8 38347 Group 4 Also applies to H8 38447 Group Table 15 28 Serial Interface SCI1 Timing VCC 2 7 V to 5 5 V AVCC 2 7 V to 5 5 V VSS AVSS 0 0 V unless otherwise indicated App...

Page 567: ...Item Symbol Min Typ Max Unit Test Condition Reference Figure Asynchronous tscyc 4 Figure 15 6 Input clock cycle Clocked synchronous 6 tcyc or tsubcyc Input clock pulse width tSCKW 0 4 0 6 tscyc Figure...

Page 568: ...upply current AISTOP1 AVCC 600 A 2 Reference value AISTOP2 AVCC 5 0 A 3 Analog input capacitance CAIN AN0 to AN11 15 0 pF Allowable signal source impedance RAIN 10 0 k Resolution data length 10 bit No...

Page 569: ...Figure Segment driver step down voltage VDS SEG1 to SEG40 0 6 V ID 2 A V1 2 7 V to 5 5 V 1 Common driver step down voltage VDC COM1 to COM4 0 3 V ID 2 A V1 2 7 V to 5 5 V 1 LCD power supply split resi...

Page 570: ...ications Values Item Symbol Min Typ Max Unit Test Conditions Programming time 1 2 4 tP 7 200 ms 128 bytes Erase time 1 3 5 tE 100 1200 ms block Reprogramming count NWEC 1000 8 10000 9 times Data retai...

Page 571: ...ws the total period for which the E bit in FLMCR1 is set It does not include the erase verification time 4 Maximum programming time tP max tP max Wait time after P bit setting z maximum number of writ...

Page 572: ...Electrical Characteristics Rev 6 00 Aug 04 2006 page 534 of 680 REJ09B0145 0600 10 This is a data retain characteristic when reprogramming is performed within the specification range including this mi...

Page 573: ...5 9 Operation Timing Figures 15 1 to 15 8 show timing diagrams t tw OSC VIH VIL tCPH tCPL tCPr OSC1 x1 EXCL tCPf Figure 15 1 Clock Input Timing RES VIL tREL Figure 15 2 RES RES RES RES Low Width VIH V...

Page 574: ...igure 15 4 UD Pin Minimum Modulation Width Timing SCK1 SO1 SI1 tscyc VIH or VOH VIL or VOL tSOD tSCKf tSCKr tSCKL tSCKH tSIS tSIH VOH VOL Note Output timing reference levels See figure 15 9 for the lo...

Page 575: ...SCK3 Input Clock Timing 32 tscyc tTXD tRXS tRXH VOH V or V IH OH V or V IL OL VOL OH CC OL SCK 31 SCK TXD31 TXD32 transmit data RXD31 RXD32 receive data Note Output timing reference levels Output high...

Page 576: ...haracteristics Rev 6 00 Aug 04 2006 page 538 of 680 REJ09B0145 0600 tCT tCSU CL1 CL2 0 4 V 0 4 V VCC 0 5 V VCC 0 5 V VCC 0 5 V 0 4 V 0 4 V DO M tCWH tCWH tCSU tCWL tSU tDH tDM tCT Figure 15 8 Segment...

Page 577: ...Section 15 Electrical Characteristics Rev 6 00 Aug 04 2006 page 539 of 680 REJ09B0145 0600 15 10 Output Load Circuit VCC 2 4 k 12 k 30 pF Output pin Figure 15 9 Output Load Condition...

Page 578: ...d Values Max 100 Max 16 pF Manufacturer Nihon Denpa Kogyo Products Name NR 18 Frequency Crystal Oscillator Parameters Figure 15 10 Resonator Equivalent Circuit Resonating Frequency Manufacturer Model...

Page 579: ...indicated However the actual electrical characteristics operating margin and noise margin may differ from the indicated values due to differences in the manufacturing process built in ROM layout patt...

Page 580: ...Section 15 Electrical Characteristics Rev 6 00 Aug 04 2006 page 542 of 680 REJ09B0145 0600...

Page 581: ...e flag in CCR Z Z zero flag in CCR V V overflow flag in CCR C C carry flag in CCR PC Program counter SP Stack pointer xx 3 8 16 Immediate data 3 8 or 16 bits d 8 16 Displacement 8 or 16 bits aa 8 16 A...

Page 582: ...8 Rs16 1 Rs16 2 0 6 MOV B aa 8 Rd B aa 8 Rd8 2 0 4 MOV B aa 16 Rd B aa 16 Rd8 4 0 6 MOV B Rs Rd B Rs8 Rd16 2 0 4 MOV B Rs d 16 Rd B Rs8 d 16 Rd16 4 0 6 MOV B Rs Rd B Rd16 1 Rd16 Rs8 Rd16 2 0 6 MOV B R...

Page 583: ...d8 decimal adjust Rd8 2 3 2 SUB B Rs Rd B Rd8 Rs8 Rd8 2 2 SUB W Rs Rd W Rd16 Rs16 Rd16 2 1 2 SUBX B xx 8 Rd B Rd8 xx 8 C Rd8 2 2 2 SUBX B Rs Rd B Rd8 Rs8 C Rd8 2 2 2 SUBS W 1 Rd W Rd16 1 Rd16 2 2 SUBS...

Page 584: ...0 2 SHLL B Rd B b7 b0 0 C 2 0 2 SHLR B Rd B b7 b0 0 C 2 0 0 2 ROTXL B Rd B C b7 b0 2 0 2 ROTXR B Rd B C b7 b0 2 0 2 ROTL B Rd B C b7 b0 2 0 2 ROTR B Rd B C b7 b0 2 0 2 BSET xx 3 Rd B xx 3 of Rd8 1 2...

Page 585: ...B Rn8 of aa 8 Rn8 of aa 8 4 8 BTST xx 3 Rd B xx 3 of Rd8 Z 2 2 BTST xx 3 Rd B xx 3 of Rd16 Z 4 6 BTST xx 3 aa 8 B xx 3 of aa 8 Z 4 6 BTST Rn Rd B Rn8 of Rd8 Z 2 2 BTST Rn Rd B Rn8 of Rd16 Z 4 6 BTST...

Page 586: ...Rd B C xx 3 of Rd8 C 2 2 BIOR xx 3 Rd B C xx 3 of Rd16 C 4 6 BIOR xx 3 aa 8 B C xx 3 of aa 8 C 4 6 BXOR xx 3 Rd B C xx 3 of Rd8 C 2 2 BXOR xx 3 Rd B C xx 3 of Rd16 C 4 6 BXOR xx 3 aa 8 B C xx 3 of aa...

Page 587: ...SP PC aa 16 4 8 JSR aa 8 SP 2 SP PC SP PC aa 8 2 8 RTS PC SP SP 2 SP 2 8 RTE CCR SP SP 2 SP PC SP SP 2 SP 2 1 0 SLEEP Transit to sleep mode 2 2 LDC xx 8 CCR B xx 8 CCR 2 2 LDC Rs CCR B Rs8 CCR 2 2 ST...

Page 588: ...ry otherwise retains value prior to arithmetic operation 4 The number of states required for execution is 4n 9 in the H8 3847R Group and 4n 8 in the H8 3847S Group H8 38347 Group and H8 38447 Group n...

Page 589: ...Table A 2 is an operation code map It shows the operation codes contained in the first byte of the instruction code bits 15 to 8 of the first instruction word Instruction when first bit of byte 2 bit...

Page 590: ...ROTL LDC BLS BTST ROTXR ROTR ORC OR BCC RTS XORC XOR BCS BSR BOR BIOR BXOR BIXOR BAND BIAND ANDC AND BNE RTE LDC BEQ NOT NEG BLD BILD BST BIST ADD SUB BVC BVS MOV INC DEC BPL JMP ADDS SUBS BMI EEPMOV...

Page 591: ...al number of states required for execution of an instruction can be calculated from these two tables as follows Execution states I SI J SJ K SK L SL M SM N SN Examples When instruction is fetched from...

Page 592: ...n Execution Status Access Location instruction cycle On Chip Memory On Chip Peripheral Module Instruction fetch SI 2 Branch address read SJ Stack operation SK Byte data access SL 2 or 3 Word data acce...

Page 593: ...s Rd 1 ADD W Rs Rd 1 ADDS ADDS W 1 Rd 1 ADDS W 2 Rd 1 ADDX ADDX B xx 8 Rd 1 ADDX B Rs Rd 1 AND AND B xx 8 Rd 1 AND B Rs Rd 1 ANDC ANDC xx 8 CCR 1 BAND BAND xx 3 Rd 1 BAND xx 3 Rd 2 1 BAND xx 3 aa 8 2...

Page 594: ...BIOR xx 3 Rd 1 BIOR xx 3 Rd 2 1 BIOR xx 3 aa 8 2 1 BIST BIST xx 3 Rd 1 BIST xx 3 Rd 2 2 BIST xx 3 aa 8 2 2 BIXOR BIXOR xx 3 Rd 1 BIXOR xx 3 Rd 2 1 BIXOR xx 3 aa 8 2 1 BLD BLD xx 3 Rd 1 BLD xx 3 Rd 2...

Page 595: ...d 2 1 BTST Rn aa 8 2 1 BXOR BXOR xx 3 Rd 1 BXOR xx 3 Rd 2 1 BXOR xx 3 aa 8 2 1 CMP CMP B xx 8 Rd 1 CMP B Rs Rd 1 CMP W Rs Rd 1 DAA DAA B Rd 1 DAS DAS B Rd 1 DEC DEC B Rd 1 DIVXU DIVXU B Rs Rd 1 12 EEP...

Page 596: ...2 1 MOV W xx 16 Rd 2 MOV W Rs Rd 1 MOV W Rs Rd 1 1 MOV W d 16 Rs Rd 2 1 MOV W Rs Rd 1 1 2 MOV W aa 16 Rd 2 1 MOV W Rs Rd 1 1 MOV W Rs d 16 Rd 2 1 MOV W Rs Rd 1 1 2 MOV W Rs aa 16 2 1 MULXU MULXU B Rs...

Page 597: ...M Internal Operation N SUB SUB B Rs Rd 1 SUB W Rs Rd 1 SUBS SUBS W 1 Rd 1 SUBS W 2 Rd 1 POP POP Rd 1 1 2 PUSH PUSH Rs 1 1 2 SUBX SUBX B xx 8 Rd 1 SUBX B Rs Rd 1 XOR XOR B xx 8 Rd 1 XOR B Rs Rd 1 XORC...

Page 598: ...rs B 1 Addresses Upper Address H F0 Bit Names Lower Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H 20 FLMCR1 SWE ESU PSU EV PV E P ROM H 21 FLMCR2 FLER H 22 FLPWCR...

Page 599: ...0 H 9B TDR31 TDR317 TDR316 TDR315 TDR314 TDR313 TDR312 TDR311 TDR310 H 9C SSR31 TDRE31 RDRF31 OER31 FER31 PER31 TEND31 MPBR31 MPBT31 H 9D RDR31 RDR317 RDR316 RDR315 RDR314 RDR313 RDR312 RDR311 RDR310...

Page 600: ...Timer G H BD ICRGF ICRGF7 ICRGF6 ICRGF5 ICRGF4 ICRGF3 ICRGF2 ICRGF1 ICRGFO H BE ICRGR ICRGR7 ICRGR6 ICRGR5 ICRGR4 ICRGR3 ICRGR2 ICRGR1 ICRGRO H BF H C0 LPCR DTS1 DTS0 CMX SGX SGS3 SGS2 SGS1 SGS0 H C1...

Page 601: ...2 PCR21 PCR20 H E6 PCR3 PCR37 PCR36 PCR35 PCR34 PCR33 PCR32 PCR31 PCR30 H E7 PCR4 PCR42 PCR41 PCR40 H E8 PCR5 PCR57 PCR56 PCR55 PCR54 PCR53 PCR52 PCR51 PCR50 H E9 PCR6 PCR67 PCR66 PCR65 PCR64 PCR63 PC...

Page 602: ...itial value Read Write 7 TMC7 0 R W 6 TMC6 0 R W 5 TMC5 0 R W 3 1 0 TMC0 0 R W 2 TMC2 0 R W 1 TMC1 0 R W 4 1 Clock select 0 Internal clock Internal clock 0 0 1 Internal clock Internal clock 1 0 1 1 0...

Page 603: ...1 Transition to erase mode Setting condition When SWE 1 and ESU 1 Program Verify 0 Program verify mode cleared initial value 1 Transition to program verify mode Setting condition When SWE 1 Erase Veri...

Page 604: ...s prohibited 7 FLER 0 R 6 0 5 0 0 0 2 0 1 0 4 0 Flash memory error 3 0 FLPWCR Flash Memory Power Control Register H F022 Flash Memory Bit Initial value Read Write 7 PDWND 0 R W 6 0 5 0 0 0 2 0 1 0 4 0...

Page 605: ...0 EB0 0 R W 2 EB2 0 R W 1 EB1 0 R W 4 EB4 0 R W Blocks 7 to 0 0 When a block of EB7 to EB0 is not selected initial value 1 When a block of EB7 to EB0 is selected 3 EB3 0 R W FENR Flash Memory Enable R...

Page 606: ...Wakeup Edge Select Register H 90 System control Bit Initial value Read Write 7 WKEGS7 0 R W 6 WKEGS6 0 R W 5 WKEGS5 0 R W 0 WKEGS0 0 R W 2 WKEGS2 0 R W 1 WKEGS1 0 R W 4 WKEGS4 0 R W WKPn edge selecte...

Page 607: ...t data is inverted TXD31 pin output data inversion switch 0 TXD31 output data is not inverted 1 TXD31 output data is inverted RXD32 pin input data inversion switch 0 RXD32 input data is not inverted 1...

Page 608: ...04 2006 page 570 of 680 REJ09B0145 0600 CWOSR Subclock Output Select Register H 92 Timer A Bit Initial value Read Write 7 1 R 6 1 R 5 1 R 0 CWOS 0 R W 2 1 R 1 1 R 4 1 R TMOW pin clock select 0 Clock...

Page 609: ...bled ECL value is held 1 ECL event clock input is enabled Count up enable H 0 ECH event clock input is disabled ECH value is held 1 ECH event clock input is enabled Channel select 0 ECH and ECL are us...

Page 610: ...s respectively of a 16 bit event counter EC Count value 7 ECH7 0 R 6 ECH6 0 R 5 ECH5 0 R 0 ECH0 0 R 2 ECH2 0 R 1 ECH1 0 R 4 ECH4 0 R 3 ECH3 0 R ECL Event Counter L H 97 AEC Bit Initial value Read Writ...

Page 611: ...1 1 clock w 2 clock 0 16 clock 64 clock Multiprocessor mode 0 Multiprocessor communication function disabled 1 Multiprocessor communication function enabled Stop bit length 0 1 stop bit 1 2 stop bits...

Page 612: ...6 page 574 of 680 REJ09B0145 0600 BRR31 Bit Rate Register 31 H 99 SCI31 Bit Initial value Read Write 7 BRR317 1 R W 6 BRR316 1 R W 5 BRR315 1 R W 4 BRR314 1 R W 3 BRR313 1 R W 0 BRR310 1 R W 2 BRR312...

Page 613: ...ta with the multiprocessor bit set to 1 is received Transmit enable 0 Transmit operation disabled TXD pin is transmit data pin 1 Transmit operation enabled TXD pin is transmit data pin Receive enable...

Page 614: ...06 page 576 of 680 REJ09B0145 0600 TDR31 Transmit Data Register 31 H 9B SCI31 Bit Initial value Read Write 7 TDR317 1 R W 6 TDR316 1 R W 5 TDR315 1 R W 4 TDR314 1 R W 3 TDR313 1 R W 0 TDR310 1 R W 2 T...

Page 615: ...or completed normally Clearing condition After reading PER31 1 cleared by writing 0 to PER31 1 A parity error has occurred during reception Setting condition Framing error 0 Reception in progress or...

Page 616: ...04 2006 page 578 of 680 REJ09B0145 0600 RDR31 Receive Data Register 31 H 9D SCI31 Bit Initial value Read Write 7 RDR317 0 R 6 RDR316 0 R 5 RDR315 0 R 4 RDR314 0 R 3 RDR313 0 R 0 RDR310 0 R 2 RDR312 0...

Page 617: ...in 1 Clock source is external clock SCK1 is input pin LATCH TAIL select 0 HOLD TAIL is output 1 LATCH TAIL is output Tail mark control 0 Tail mark is not output synchronous mode 1 Tail mark is output...

Page 618: ...rts transfer operation 1 Read Write Read Write Note Only a write of 0 for flag clearing is possible 0 Clearing condition After reading ORER 1 cleared by writing 0 to ORER 1 Setting condition When an e...

Page 619: ...R W Used for transmit data setting and receive data storage 8 bit transfer mode Not used 16 bit transfer mode Upper 8 bits of data register SDRL Serial Data Register L H A3 SCI1 Bit Initial value Rea...

Page 620: ...1 1 clock w 2 clock 0 16 clock 64 clock Multiprocessor mode 0 Multiprocessor communication function disabled 1 Multiprocessor communication function enabled Stop bit length 0 1 stop bit 1 2 stop bits...

Page 621: ...page 583 of 680 REJ09B0145 0600 BRR32 Bit Rate Register 32 H A9 SCI32 Bit Initial value Read Write 7 BRR327 1 R W 6 BRR326 1 R W 5 BRR325 1 R W 4 BRR324 1 R W 3 BRR323 1 R W 0 BRR3120 1 R W 2 BRR322...

Page 622: ...ta with the multiprocessor bit set to 1 is received Transmit enable 0 Transmit operation disabled TXD pin is transmit data pin 1 Transmit operation enabled TXD pin is transmit data pin Receive enable...

Page 623: ...06 page 585 of 680 REJ09B0145 0600 TDR32 Transmit Data Register 32 H AB SCI32 Bit Initial value Read Write 7 TDR327 1 R W 6 TDR326 1 R W 5 TDR325 1 R W 4 TDR324 1 R W 3 TDR323 1 R W 0 TDR320 1 R W 2 T...

Page 624: ...s or completed normally Clearing condition After reading PER32 1 cleared by writing 0 to PER32 1 A parity error has occurred during reception Setting condition Framing error 0 Reception in progress or...

Page 625: ...04 2006 page 587 of 680 REJ09B0145 0600 RDR32 Receive Data Register 32 H AD SCI32 Bit Initial value Read Write 7 RDR327 0 R 6 RDR326 0 R 5 RDR325 0 R 4 RDR324 0 R 3 RDR323 0 R 0 RDR320 0 R 2 RDR322 0...

Page 626: ...R W 2 TMA2 0 R W 1 TMA1 0 R W Internal clock select TMA3 TMA2 0 PSS PSS PSS PSS 0 4 1 Clock output select 0 32 16 TMA1 0 1 TMA0 0 0 0 0 0 0 1 0 1 0 0 0 1 PSS PSS PSS PSS 1 0 1 0 0 1 0 0 1 0 1 0 1 1 1...

Page 627: ...Registers Rev 6 00 Aug 04 2006 page 589 of 680 REJ09B0145 0600 TCA Timer Counter A H B1 Timer A Bit Initial value Read Write 7 TCA7 0 R 6 TCA6 0 R 5 TCA5 0 R 4 TCA4 0 R 3 TCA3 0 R 0 TCA0 0 R 2 TCA2 0...

Page 628: ...ST Bit 0 write inhibit 0 Bit 0 is write enabled Bit 0 is write protected 1 Watchdog timer on 0 Watchdog timer operation is disabled Watchdog timer operation is enabled 1 Bit 2 write inhibit 0 Bit 2 is...

Page 629: ...MC0 0 R W 2 TMC2 0 R W 1 TMC1 0 R W 4 1 Auto reload function select Clock select Internal clock Internal clock 0 1 Internal clock Internal clock 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 Internal cl...

Page 630: ...a read the TCC value is read 7 TCC7 0 R 6 TCC6 0 R 5 TCC5 0 R 4 TCC4 0 R 3 TCC3 0 R 0 TCC0 0 R 2 TCC2 0 R 1 TCC1 0 R Count value TLC Timer Load Register C H B5 Timer C Bit Initial value Read Write No...

Page 631: ...W Clock select L 0 Counting on external event TMIF rising falling edge Internal clock 32 Internal clock 16 Internal clock 4 Internal clock w 4 1 1 1 1 0 0 1 1 0 1 0 1 Toggle output level L 0 Low level...

Page 632: ...ition After reading CMFL 1 cleared by writing 0 to CMFL 1 Setting condition Set when the TCFL value matches the OCRFL value Timer overflow flag L 0 Clearing condition After reading OVFL 1 cleared by w...

Page 633: ...r Counter FL H B9 Timer F Bit Initial value Read Write Note TCFH and TCFL can also be used as the upper and lower halves respectively of a 16 bit timer counter TCF 7 TCFL7 0 R W 6 TCFL6 0 R W 5 TCFL5...

Page 634: ...mpare Register FL H BB Timer F Bit Initial value Read Write Note OCRFH and OCRFL can also be used as the upper and lower halves respectively of a 16 bit output compare register OCRF 7 OCRFL7 1 R W 6 O...

Page 635: ...nterrupt request is disabled TCG overflow interrupt request is enabled 0 1 0 Clearing condition After reading OVFH 1 cleared by writing 0 to OVFH 1 Setting condition Set when TCG overflows from H FF t...

Page 636: ...at falling edge of input capture signal 7 ICRGF7 0 R 6 ICRGF6 0 R 5 ICRGF5 0 R 4 ICRGF4 0 R 3 ICRGF3 0 R 0 ICRGF0 0 R 2 ICRGF2 0 R 1 ICRGF1 0 R ICRGR Input Capture Register GR H BE Timer G Bit Initial...

Page 637: ...o SEG9 Port Port Port Port Port SEG Port Notes Initial value Don t care SEG8 to SEG1 Duty select common function select Expansion signal select Bit 7 DTS1 0 0 0 0 1 1 1 1 Bit 6 DTS0 0 0 1 1 0 0 1 1 Bi...

Page 638: ...e power supply on off control Frame frequency select Operating Clock Bit 1 Bit 2 Bit 3 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Bit 1 CKS1 CKS2 CKS3 CKS0 w w 2 w...

Page 639: ...5 1 3 CDS3 0 R W 0 CDS0 0 R W 2 CDS2 0 R W 1 CDS1 0 R W 4 0 R W A waveform B waveform switching control Charge discharge pulse duty cycle select Duty Cycle Bit 1 Bit 2 Bit 3 0 0 0 0 0 0 0 0 1 1 0 0 0...

Page 640: ...D Result Register L H C5 Bit Initial value Read Write ADRRH 7 ADR9 Undefined R 6 ADR8 Undefined R 5 ADR7 Undefined R 3 ADR5 Undefined R 0 ADR2 Undefined R 2 ADR4 Undefined R 1 ADR3 Undefined R 4 ADR6...

Page 641: ...0 Bit 2 Analog Input Channel Don t care CH3 CH2 0 CH1 CH0 Bit 1 Bit 0 0 AN 1 1 0 1 1 0 0 1 0 1 0 1 1 1 0 0 External trigger select 0 Disables start of A D conversion by external trigger 1 Enables sta...

Page 642: ...5 0600 ADSR A D Start Register H C7 A D converter Bit Initial value Read Write 7 ADSF 0 R W 6 1 5 1 4 1 3 1 0 1 2 1 1 1 A D status flag 0 1 Read Write Read Write Indicates completion of A D conversion...

Page 643: ...P12 I O pin 1 Functions as TMOFH output pin P13 TMIG pin function switch 0 Functions as P13 I O pin 1 Functions as TMIG input pin P14 IRQ4 ADTRG pin function switch 0 Functions as P14 I O pin 1 Functi...

Page 644: ...ite 7 1 6 1 4 1 3 1 0 SCK1 0 R W 2 SO1 0 R W 1 SI1 0 R W 5 POF1 0 R W P20 SCK1 pin function switch 0 Functions as P20 I O pin Functions as SCK1 I O pin 1 P22 SO1 pin function switch 0 Functions as P22...

Page 645: ...1 0 R W P20 SCK1 pin function switch 0 Functions as P20 I O pin Functions as SCK1 I O pin 1 P22 SO1 pin function switch 0 Functions as P22 I O pin Functions as SO1 output pin 1 P21 SI1 pin function sw...

Page 646: ...O pin 1 Functions as PWM output pin P32 RESO pin function switch 0 Functions as P32 I O pin 1 Functions as RESO I O pin P43 IRQ0 pin function switch 0 Functions as P43 I O pin 1 Functions as IRQ0 inp...

Page 647: ...OD4 0 R W 3 NMOD3 0 R W 0 NMOD0 0 R W 2 NMOD2 0 R W 1 NMOD1 0 R W 0 P2n is CMOS output n 7 to 0 1 P2n is NMOS open drain output PMR5 Port Mode Register 5 H CC I O port Bit Initial value Read Write 7 W...

Page 648: ...t 8 The conversion period is 65 536 with a minimum modulation width of 4 The input clock is 16 t 16 The conversion period is 131 072 with a minimum modulation width of 8 Note t Period of PWM input clo...

Page 649: ...Initial value Read Write 7 P27 0 R W 6 P26 0 R W 5 P25 0 R W 4 P24 0 R W 3 P23 0 R W 0 P20 0 R W 2 P22 0 R W 1 P21 0 R W Data for port 2 pins PDR3 Port Data Register 3 H D6 I O ports Bit Initial valu...

Page 650: ...l value Read Write 7 P6 0 R W 6 P6 0 R W 5 P6 0 R W 4 P6 0 R W 3 P6 0 R W 0 P6 0 R W 2 P6 0 R W 1 P6 0 R W 3 0 2 1 4 5 6 7 Data for port 6 pins PDR7 Port Data Register 7 H DA I O ports Bit Initial val...

Page 651: ...R W Data for port 9 pins PDRA Port Data Register A H DD I O ports Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 PA 0 R W 0 PA 0 R W 2 PA 0 R W 1 PA 0 R W 3 0 2 1 Data for port A pins PDRB Port Data R...

Page 652: ...nput pull up MOS is off Input pull up MOS is on Port 1 input pull up MOS control Note When the PCR1 specification is 0 Input port specification PUCR3 Port Pull Up Control Register 3 H E1 I O ports Bit...

Page 653: ...nput pull up MOS is off Input pull up MOS is on Port 5 input pull up MOS control Note When the PCR5 specification is 0 Input port specification PUCR6 Port Pull Up Control Register 6 H E3 I O ports Bit...

Page 654: ...pin 1 Output pin 7 6 5 4 3 2 1 0 PCR2 Port Control Register 2 H E5 I O ports Bit Initial value Read Write 7 PCR27 0 W 6 PCR26 0 W 5 PCR25 0 W 4 PCR24 0 W 3 PCR23 0 W 0 PCR20 0 W 2 PCR22 0 W 1 PCR21 0...

Page 655: ...0 2 1 PCR5 Port Control Register 5 H E8 I O ports Bit Initial value Read Write 7 PCR5 0 W 6 PCR5 0 W 5 PCR5 0 W 4 PCR5 0 W 3 PCR5 0 W 0 PCR5 0 W 2 PCR5 0 W 1 PCR5 0 W Port 5 input output select 0 Inp...

Page 656: ...pin 1 Output pin 7 6 5 4 3 2 1 0 PCR8 Port Control Register 8 H EB I O ports Bit Initial value Read Write 7 PCR8 0 W 6 PCR8 0 W 5 PCR8 0 W 4 PCR8 0 W 3 PCR8 0 W 0 PCR8 0 W 2 PCR8 0 W 1 PCR8 0 W Port 8...

Page 657: ...00 Aug 04 2006 page 619 of 680 REJ09B0145 0600 PCRA Port Control Register A H ED I O ports Bit Initial value Read Write 7 0 6 0 5 0 4 0 3 PCRA 0 W 0 PCRA 0 W 2 PCRA 0 W 1 PCRA 0 W 0 1 2 3 Port A input...

Page 658: ...16 384 states 0 0 1 Wait time 32 768 states Wait time 65 536 states 1 0 1 Active medium speed mode clock select 16 32 0 1 0 0 1 1 64 128 1 1 0 0 1 0 1 Wait time 131 072 states Wait time 2 states Wait...

Page 659: ...cuted in active high speed mode a direct transition is made to active medium speed mode if SSBY 0 MSON 1 and LSON 0 or to subactive mode if SSBY 1 TMA3 1 and LSON 1 When a SLEEP instruction is execute...

Page 660: ...Rising edge of IRQ0 pin input is detected 1 IRQ1 edge select 0 Falling edge of IRQ1 TMIC pin input is detected Rising edge of IRQ1 TMIC pin input is detected 1 IRQ2 edge select 0 Falling edge of IRQ2...

Page 661: ...R W 1 IEN1 0 R W 5 IENWP 0 R W IRQ4 to IRQ0 interrupt enable 0 Disables IRQ4 to IRQ0 interrupt requests Enables IRQ4 to IRQ0 interrupt requests 1 Wakeup interrupt enable 0 Disables WKP7 to WKP0 interr...

Page 662: ...interrupt enable 0 Disables timer FL interrupt requests 1 Enables timer FL interrupt requests Timer FH interrupt enable 0 Disables timer FH interrupt requests 1 Enables timer FH interrupt requests Tim...

Page 663: ...n IRRIn 1 it is cleared by writing 0 n 4 to 0 Note Bits 7 6 and 4 to 0 can only be written with 0 for flag clearing 1 Setting condition When pin IRQn is designated for interrupt input and the designat...

Page 664: ...Clearing condition When IRRDT 1 it is cleared by writing 0 1 Setting condition When a SLEEP instruction is executed while DTON is set to 1 and a direct transition is made Timer FH interrupt request f...

Page 665: ...WPF7 0 R W 6 IWPF6 0 R W 5 IWPF5 0 R W 3 IWPF3 0 R W 0 IWPF0 0 R W 2 IWPF2 0 R W 1 IWPF1 0 R W 4 IWPF4 0 R W 0 Clearing condition When IWPFn 1 it is cleared by writing 0 n 7 to 0 Note All bits can onl...

Page 666: ...e Timer G module standby mode is cleared 1 A D converter module standby mode control 0 A D converter is set to module standby mode A D converter module standby mode is cleared 1 Timer C module standby...

Page 667: ...de control WDT module standby mode control 0 WDT is set to module standby mode WDT module standby mode is cleared 1 Asynchronous event counter module standby mode control 0 Asynchronous event counter...

Page 668: ...Block Diagrams of Port 1 VCC VCC VSS PUCR1n PMR1n PDR1n PCR1n IRQn 4 n SBY low level during reset and in standby mode Internal data bus Port data register 1 Port control register 1 Port mode register...

Page 669: ...ix C I O Port Block Diagrams Rev 6 00 Aug 04 2006 page 631 of 680 REJ09B0145 0600 VCC VCC SBY VSS PUCR13 PMR13 PDR13 PCR13 Timer G module TMIG Internal data bus P13 Figure C 1 b Port 1 Block Diagram P...

Page 670: ...0145 0600 VCC VCC VSS PUCR1n PMR1n PDR1n PCR1n SBY Internal data bus PDR1 PCR1 PMR1 PUCR1 n 2 1 Port data register 1 Port control register 1 Port mode register 1 Port pull up control register 1 TMOFH...

Page 671: ...f 680 REJ09B0145 0600 VCC VCC VSS PUCR10 PMR10 PDR10 PCR10 SBY Internal data bus PDR1 PCR1 PMR1 PUCR1 Port data register 1 Port control register 1 Port mode register 1 Port pull up control register 1...

Page 672: ...k Diagrams of Port 2 P2n VCC PDR2n PCR2n SBY VSS PDR2 Port data register 2 PCR2 Port control register 2 PMR4 Port mode register 4 n 7 to 3 PMR4n Internal data bus Figure C 2 a 1 Port 2 Block Diagram P...

Page 673: ...600 P24 VCC PDR24 PCR24 SBY Reset signal low level during reset VSS PDR2 Port data register 2 PCR2 Port control register 2 PMR4 Port mode register 4 PMR44 Internal data bus VCC Figure C 2 a 2 Port 2 B...

Page 674: ...ge 636 of 680 REJ09B0145 0600 P22 VCC PMR25 SCI1 module PMR42 PMR22 PDR22 PCR22 SBY VSS Internal data bus PDR2 Port data register 2 PCR2 Port control register 2 PMR2 Port mode register 2 PMR4 Port mod...

Page 675: ...6 page 637 of 680 REJ09B0145 0600 P21 VCC PMR41 PMR21 PDR21 PCR21 SCI module SBY VSS SI Internal data bus PDR2 Port data register 2 PCR2 Port control register 2 PMR2 Port mode register 2 PMR4 Port mod...

Page 676: ...638 of 680 REJ09B0145 0600 P20 VCC PMR40 PMR20 PDR20 PCR20 SBY VSS Internal data bus PDR2 Port data register 2 PCR2 Port control register 2 PMR2 Port mode register 2 PMR4 Port mode register 4 EXCK SC...

Page 677: ...lock Diagrams of Port 3 P3n VCC VCC PUCR3n PMR3n PDR3n PCR3n AEC module Internal data bus SBY VSS AEVH P36 AEVL P37 PDR3 PCR3 PMR3 PUCR3 Port data register 3 Port control register 3 Port mode register...

Page 678: ...45 0600 P35 SCI31 module PDR35 PUCR35 SCINV1 PCR35 SBY VSS PDR3 Port data register 3 PCR3 Port control register 3 PUCR3 Port pull up control register 3 SCINV1 Bit 1 of serial port control register SPC...

Page 679: ...45 0600 P34 VCC VCC SCI31 module PDR34 PCR34 SCINV0 SBY VSS PDR3 Port data register 3 PCR3 Port control register 3 PUCR3 Port pull up control register 3 SCINV0 Bit 0 of serial port control register SP...

Page 680: ...642 of 680 REJ09B0145 0600 P33 VCC SCI31 module PDR33 PCR33 SBY VSS PDR3 Port data register 3 PCR3 Port control register 3 PUCR3 Port pull up control register 3 SCKIE31 SCKOE31 SCKO31 SCKI31 Internal...

Page 681: ...9B0145 0600 P32 VCC VCC PUCR32 Internal data bus PMR32 PDR32 PCR32 SBY VSS PDR3 Port data register 3 PCR3 Port control register 3 PMR3 Port mode register 3 PUCR3 Port pull up control register 3 RESO F...

Page 682: ...J09B0145 0600 P32 VCC VCC PUCR32 Internal data bus PMR32 PDR32 PCR32 SBY VSS PDR3 Port data register 3 PCR3 Port control register 3 PMR3 Port mode register 3 PUCR3 Port pull up control register 3 Figu...

Page 683: ...0600 VCC VCC VSS PUCR31 PDR31 PCR31 UD SBY Internal data bus PDR3 PCR3 PMR3 PUCR3 Port data register 3 Port control register 3 Port mode register 3 Port pull up control register 3 P31 Timer C module P...

Page 684: ...R31 UD PMR27 SBY Internal data bus PDR3 PCR3 PMR2 PMR3 PUCR3 Port data register 3 Port control register 3 Port mode register 2 Port mode register 3 Port pull up control register 3 P31 Timer C module P...

Page 685: ...7 of 680 REJ09B0145 0600 P30 VCC VCC PUCR30 PMR30 PDR30 PCR30 SBY VSS PDR3 Port data register 3 PCR3 Port control register 3 PMR3 Port mode register 3 PUCR3 Port pull up control register 3 PWM PWM mod...

Page 686: ...C I O Port Block Diagrams Rev 6 00 Aug 04 2006 page 648 of 680 REJ09B0145 0600 C 4 Block Diagrams of Port 4 P43 PMR33 Internal data bus IRQ0 PMR3 Port mode register 3 Figure C 4 a Port 4 Block Diagram...

Page 687: ...page 649 of 680 REJ09B0145 0600 P42 SCI32 module Internal data bus PDR42 SCINV3 PCR42 SBY VSS PDR4 Port data register 4 PCR4 Port control register 4 SCINV3 Bit 3 of serial port control register SPCR T...

Page 688: ...page 650 of 680 REJ09B0145 0600 P41 VCC SCI32 module PDR41 PCR41 SBY VSS PDR4 Port data register 4 PCR4 Port control register 4 SCINV2 Bit 2 of serial port control register SPCR RE32 RXD32 Internal da...

Page 689: ...v 6 00 Aug 04 2006 page 651 of 680 REJ09B0145 0600 P40 VCC SCI32 module PDR40 PCR40 SBY VSS PDR4 Port data register 4 PCR4 Port control register 4 SCKIE32 SCKOE32 SCKO32 Internal data bus SCKI32 Figur...

Page 690: ...REJ09B0145 0600 C 5 Block Diagram of Port 5 P5n VCC VCC PUCR5n Internal data bus PMR5n PDR5n PCR5n SBY VSS WKPn PDR5 Port data register 5 PCR5 Port control register 5 PMR5 Port mode register 5 PUCR5 P...

Page 691: ...06 page 653 of 680 REJ09B0145 0600 C 6 Block Diagram of Port 6 P6n VCC VCC PUCR6n PDR6n Internal data bus PCR6n SBY VSS PDR6 Port data register 6 PCR6 Port control register 6 PUCR6 Port pull up contro...

Page 692: ...grams Rev 6 00 Aug 04 2006 page 654 of 680 REJ09B0145 0600 C 7 Block Diagram of Port 7 P7n VCC PDR7n Internal data bus PCR7n SBY VSS PDR7 Port data register 7 PCR7 Port control register 7 n 7 to 0 Fig...

Page 693: ...grams Rev 6 00 Aug 04 2006 page 655 of 680 REJ09B0145 0600 C 8 Block Diagrams of Port 8 P8n VCC PDR8n Internal data bus PCR8n SBY VSS PDR8 PCR8 n 7 to 0 Port data register 8 Port control register 8 Fi...

Page 694: ...grams Rev 6 00 Aug 04 2006 page 656 of 680 REJ09B0145 0600 C 9 Block Diagram of Port 9 P9n VCC PDR9n PCR9n SBY VSS Internal data bus PDR9 Port data register 9 PCR9 Port control register 9 n 7 to 0 Fig...

Page 695: ...rams Rev 6 00 Aug 04 2006 page 657 of 680 REJ09B0145 0600 C 10 Block Diagram of Port A PAn VCC PDRAn Internal data bus PCRAn SBY VSS PDRA Port data register A PCRA Port control register A n 3 to 0 Fig...

Page 696: ...ix C I O Port Block Diagrams Rev 6 00 Aug 04 2006 page 658 of 680 REJ09B0145 0600 C 11 Block Diagram of Port B PBn Internal data bus AMR3 to AMR0 A D module VIN n 7 to 0 DEC Figure C 11 Port B Block D...

Page 697: ...dix C I O Port Block Diagrams Rev 6 00 Aug 04 2006 page 659 of 680 REJ09B0145 0600 C 12 Block Diagram of Port C PCn DEC A D module AMR3 to 0 VIN n 3 to 0 Internal data bus Figure C 12 Port C Block Dia...

Page 698: ...ns P67 to P60 High impedance Retained Retained High impedance Retained Functions Functions P77 to P70 High impedance Retained Retained High impedance Retained Functions Functions P87 to P80 High imped...

Page 699: ...HD6433843R H 100 pin QFP FP 100B Regular products HD6433843RF HD6433843R F 100 pin QFP FP 100A Mask ROM versions HD6433843RX HD6433843R X 100 pin TQFP TFP 100B HD6433843RW HD6433843R W 100 pin TQFP TF...

Page 700: ...D6433846R H 100 pin QFP FP 100B HD6433846RE HD6433846R F 100 pin QFP FP 100A HD6433846RL HD6433846R X 100 pin TQFP TFP 100B Wide range specifi cation products HD6433846RWI HD6433846R W 100 pin TQFP TF...

Page 701: ...Die HD6433845SD HD6433845S H 100 pin QFP FP 100B HD6433845SL HD6433845S X 100 pin TQFP TFP 100B Wide range specifi cation products HD6433845SWI HD6433845S W 100 pin TQFP TFP 100G H8 3846S HD6433846SH...

Page 702: ...TQFP TFP 100B HCD64338343 Die HD64338343HW 38343H 100 pin QFP FP 100B HD64338343WW 38343W 100 pin TQFP TFP 100G Wide range specifi cation products HD64338343XW 38343X 100 pin TQFP TFP 100B H8 38344 HD...

Page 703: ...TQFP TFP 100B HCD64338346 Die HD64338346HW 38346H 100 pin QFP FP 100B HD64338346WW 38346W 100 pin TQFP TFP 100G Wide range specifi cation products HD64338346XW 38346X 100 pin TQFP TFP 100B H8 38347 H...

Page 704: ...TQFP TFP 100B HCD64338443 Die HD64338443HW 38443H 100 pin QFP FP 100B HD64338443WW 38443W 100 pin TQFP TFP 100G Wide range specifi cation products HD64338443XW 38443X 100 pin TQFP TFP 100B H8 38444 HD...

Page 705: ...38446 Die HD64338446HW 38446H 100 pin QFP FP 100B HD64338446WW 38446W 100 pin TQFP TFP 100G Wide range specifi cation products HD64338446XW 38446X 100 pin TQFP TFP 100B H8 38447 HD64338447H 38447H 100...

Page 706: ...ASH 2 DIMENSION 3 DOES NOT INCLUDE TRIM OFFSET PRQP0100JE B P QFP100 14x20 0 65 0 83 0 58 0 15 0 13 0 65 10 0 19 2 18 8 18 4 3 10 0 12 0 17 0 22 0 24 0 32 0 40 0 00 0 30 0 15 0 20 0 30 20 14 L D 1 E D...

Page 707: ...s section p 1 1 c b c b 2 1 1 Detail F c A A L L A PRQP0100KA A P QFP100 14x14 0 50 1 0 1 0 0 08 0 10 0 5 8 0 0 25 0 12 0 15 0 20 0 00 0 27 0 22 0 17 0 22 0 17 0 12 3 05 16 3 16 0 15 7 1 E D 1 1 p 1 E...

Page 708: ...20 1 20 0 20 0 10 0 00 0 27 0 22 0 17 0 22 0 17 0 12 1 E D 1 1 p 1 E D 2 L Z Z y x c b b A H A E D A c e e L H MASS Typ 0 5g TFP 100B TFP 100BV RENESAS Code JEITA Package Code Previous Code 0 6 0 5 0...

Page 709: ...ail F c A A L A L Terminal cross section 1 1 p b c c b PTQP0100LC A P TQFP100 12x12 0 40 H L e e c A D E A H A b b c x y Z Z L 2 D E 1 p 1 1 D E 1 MASS Typ 0 4g Reference Symbol Dimension in Millimete...

Page 710: ...n in figure G 1 X direction Y direction 6 10 0 05 6 23 0 05 0 28 0 22 X direction Y direction 6 10 0 25 6 23 0 25 Maximum plain Max 0 03 Unit mm Figure G 1 Chip Sectional Figure The specifications of...

Page 711: ...ection Y direction 4 35 0 25 4 83 0 25 Maximum plain Pattern side Chip back Max 0 03 Unit mm Figure G 3 Chip Sectional Figure The specifications of the chip form of the H8 38347 Group Mask ROM version...

Page 712: ...0 REJ09B0145 0400 Appendix H Form of Bonding Pads The form of the bonding pads for the HCD6433847R HCD6433846R HCD6433845R HCD6433844R HCD6433843R and HCD6433842R is shown in figure H 1 Bonding area M...

Page 713: ...6 00 Aug 04 2006 page 675 of 680 REJ09B0145 0600 The form of the bonding pads for the HCD6433847S HCD6433846S HCD6433845S and HCD6433844S is shown in figure H 2 Bonding area Metal Layer 75 m 75 m 2 5...

Page 714: ...age 676 of 680 REJ09B0145 0400 The form of the bonding pads for the HCD64F38347 HCD64F38447 H8 38347 Group Mask ROM version and H8 38447 Group Mask ROM version is shown in figure H 3 Bonding area Meta...

Page 715: ...33845R HCD6433844R HCD6433843R and HCD6433842R are shown in figure I 1 51 51 Chip tray code name Manufactured by DAINIPPON INK AND CHEMICALS INCORPORATED Code name CT054 Characteristic engraving TCT06...

Page 716: ...6433844S are shown in figure I 2 51 51 Chip tray code name Manufactured by DAINIPPON INK AND CHEMICALS INCORPORATED Code name CT065 Characteristic engraving TCT4040 060 Chip orientation Chip Type code...

Page 717: ...the HCD64F38347 and HCD64F38447 are shown in figure I 3 Type code Chip orientation Chip 4 83 4 35 Chip tray code name Code name CT037 Characteristic engraving 2CT049049 070 5 4 0 1 4 9 0 05 X 6 6 0 1...

Page 718: ...k ROM version and H8 38447 Group Mask ROM version are shown in figure I 4 Type code Chip orientation Chip 3 77 3 55 Chip tray code name Code name CT127 Characteristic engraving 2CT040040 063 5 5 0 1 4...

Page 719: ...447 Group Publication Date 1st Edition September 1999 Rev 6 00 August 04 2006 Published by Sales Strategic Planning Div Renesas Technology Corp Edited by Customer Support Department Global Strategic C...

Page 720: ...Renesas Technology Hong Kong Ltd 7th Floor North Tower World Finance Centre Harbour City 1 Canton Road Tsimshatsui Kowloon Hong Kong Tel 852 2265 6688 Fax 852 2730 6071 Renesas Technology Taiwan Co L...

Page 721: ...1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan H8 3847R Group H8 3847S Group H8 38347 Group H8 38447 Group REJ09B0145 0600 Hardware Manual...

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