Renesas H8/38342, Hardware Manual

Page: 399 / 721

Section 10 Serial Communication Interface
Rev. 6.00 Aug 04, 2006 page 361 of 680
REJ09B0145-0600
Bit 7: Transmit data register empty (TDRE)
Bit 7 indicates that transmit data has been transferred from TDR to TSR.
Bit 7
TDRE
Description
0 Transmit data written in TDR has not been transferred to TSR
Clearing conditions:
After reading TDRE = 1, cleared by writing 0 to TDRE
When data is written to TDR by an instruction
1 Transmit data has not been written to TDR, or transmit data written in
TDR has been transferred to TSR
Setting conditions:
When bit TE in SCR3 is cleared to 0
When data is transferred from TDR to TSR
(initial value)
Bit 6: Receive data register full (RDRF)
Bit 6 indicates that received data is stored in RDR.
Bit 6
RDRF
Description
0 There is no receive data in RDR
Clearing conditions:
After reading RDRF = 1, cleared by writing 0 to RDRF
When RDR data is read by an instruction (initial value)
1 There is receive data in RDR
Setting condition:
When reception ends normally and receive data is transferred from RSR to RDR
Note: If an error is detected in the receive data, or if the RE bit in SCR3 has been cleared to 0,
RDR and bit RDRF are not affected and retain their previous state.
Note that if data reception is completed while bit RDRF is still set to 1, an overrun error
(OER) will result and the receive data will be lost.