2
Hardware Description
38
The
platform
reset
signal
originates
in
the
PCH.
The
potential
sources
or
triggers
of
a
platform
reset
include:
•
The
front
panel
Reset
button
•
A
reset
assertion
generated
over
the
board
debug
header
during
a
troubleshooting
session
•
An
IPMC
reset
command
generated
due
to
one
of
the
following
events:
•
Watchdog
timer
expiration
•
An
MR
reset
is
asserted
(by
either
the
PCH
or
the
IPMC)
but
they
are
disabled
in
the
CC
FPGA.
In
this
case
it
reverts
to
a
platform
reset.
Powergood reset
A
powergood
reset
is
similar
to
a
platform
reset,
except
that
all
sticky
bits
in
the
CPU
and
PCH
are
cleared.
For
the
CPUs,
a
powergood
reset
will
result
in
reset
of
all
the
states
in
the
processor,
including
the
sticky
state
that
is
preserved
on
the
other
resets.
There
is
a
“Powergood
Reset”
enable
bit
in
the
reset
control
register
of
the
CC
FPGA.
When
this
bit
is
set,
all
platform
resets
are
converted
to
Powergood
resets.
In
other
words,
when
this
bit
is
set,
any
of
the
sources
or
triggers
that
would
otherwise
cause
a
platform
reset
will
instead
cause
a
powergood
reset.
There
is
a
second
enable
bit
in
the
CC
FPGA,
that
when
set
also
asserts
Powergood
Reset,
normally
from
the
BIOS.
Memory-Retained (MR) reset
A
memory
‐
retained
reset
will
preserve
the
contents
of
main
memory
while
the
rest
of
the
system
experiences
a
Platform
Reset.
The
intended
usage
for
MR
‐
Reset
is
to
provide
an
operating
system
kernel
crash
dump
location,
so
that
debug
information
can
be
recovered
after
an
OS
crash.
When
an
MR
‐
Reset
is
initiated
from
one
of
the
sources,
the
result
is
an
INIT*
virtual
legacy
wire
(VLW)
message
sent
to
the
CPUs
from
the
PCH.
INIT*
triggers
the
BIOS
to
run
from
the
reset
vector
in
the
shadowed
F000
segment,
where
the
MR
‐
Reset
code
is
stored.
If
a
valid
signature
exists
in
this
location
(i.e.
MR
‐
Reset
has
been
enabled
in
the
BIOS
setup
menu)
then
the
MR
‐
Reset
code
is
executed.
The
INIT*
sequence
has
PCH
drive
the
INIT*
VLW
message
to
the
CPUs
and
the
INIT_3_3V*
signal
to
the
CC
FPGA.
The
MR
‐
Reset
BIOS
code
puts
the
system
into
the
S3
sleep
state.
In
S3,
the
internal
memory
controller
for
each
CPU
places
all
the
DIMMs
on
the
associated
memory
channels
into
self
‐
refresh
and
the
PCH
asserts
the
PLTRST*
signal.
The
RTC
alarm
in
the
PCH
is
used
to
wake
the
system
up
from
S3,
causing
the
PCH
to
de
‐
assert
PLTRST*.
The
BIOS
uses
the
S3
resume
path
and
skips
over
memory
initialization.
This
method
allows
the
contents
of
the
DIMMs
to
remain
valid
while
the
system
is
reset.
