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C
Pinouts and Mapping
111
Zone 1 P10 connector pinout
Table 44
lists
the
P10
connector
pinout.
Table 44. Zone 1 contact assignments, P10
Contact Designation
Description
Mating sequence
1
Reserved
Reserved
not applicable
2
Reserved
Reserved
not applicable
3
Reserved
Reserved
not applicable
4
Reserved
Reserved
not applicable
5
HA0
Hardware Address Bit 0
Third
6
HA1
Hardware Address Bit 1
Third
7
HA2
Hardware Address Bit 2
Third
8
HA3
Hardware Address Bit 3
Third
9
HA4
Hardware Address Bit 4
Third
10
HA5
Hardware Address Bit 5
Third
11
HA6
Hardware Address Bit 6
Third
12
HA7/P
Hardware Address Bit 7 (Odd Parity Bit)
Third
13
SCL_A
IPMB Clock, Port A
Third
14
SDA_A
IPMB Data, Port A
Third
15
SCL_B
IPMB Clock, Port B
Third
16
SDA_B
IPMB Data, Port B
Third
17
18
19
20
21
22
23
24
25
SHELF_GND
Shelf Ground (Connection to Shelf Ground and safety ground)
First
26
LOGIC_GND
Logic Ground (Ground reference and return for front blade-to-front blade logic signals)
First
27
ENABLE_B
Enable B (Short pin for power sequencing, Feed B, tied to VRTN_B on Backplane)
Fourth
28
VRTN_A
Voltage Return A (–48 Volt return, Feed A)
First
29
VRTN_B
Voltage Return B (–48 Volt return, Feed B)
First
30
EARLY_A
–48 Volt Early A (–48 Volt input, Feed A precharge)
First
31
EARLY_B
–48 Volt Early B (–48 Volt input, Feed B precharge)
First
32
ENABLE_A
Enable A (Short pin for power sequencing, Feed A, tied to VRTN_A on Backplane)
Fourth
33
–48V_A
–48 Volt A (–48 Volt input, Feed A, uses ENABLE_A to enable converters)
Second
34
–48V_B
–48 Volt B (–48 Volt input, Feed B, uses ENABLE_B to enable converters)
Third
Gray indicates unused pins