2
Hardware Description
27
QuickPath Interconnect (QPI)
The
Quickpath
interconnect
(QPI)
provides
a
point
‐
to
‐
point
contact
between
the
E5
‐
2400
family
processors.
The
QPI
interface
is
20
lanes
wide
under
full
operation
and
is
the
communication
path
between
the
CPUs.
Data
of
any
width
is
converted
to
packets
and
then
sent
serially
over
the
QPI
link.
The
E5
‐
2400
supports
QPI
speeds
of
6.4
GT/s
to
8.0
GT/s
depending
on
the
installed
processor.
PCI Express
The
integrated
I/O
module
on
each
E5
‐
2400
family
processor
provides
24
PCI
Express
lanes
that
are
capable
of
Gen1
(2.5
GT/s),
Gen2
(5.0
GT/s)
and
Gen3
(8.0
GT/s)
speeds.
The
lanes
are
split
into
a
x16
and
a
x8
port
and
both
can
be
divided
into
x8,
x4,
x2
and
x1
ports.
CPU0
also
uses
a
Gen
2
Direct
Media
Interface
(DMI)
port
that
can
be
configured
for
either
DMI
for
PCH
connectivity
or
used
as
a
Gen2
x4
PCI
Express
port.
Table 7
shows
the
PCI
Express
port
mapping
for
each
CPU
on
the
CPM.
Memory
The
CPM
uses
memory
such
as
the
built
‐
in
processor
cache,
standard
RAM,
and
memory
external
to
any
of
the
existing
board
components.
The
CPM
supports
the
following
types
of
memory:
•
DIMM
memory
‐
Registered
Dual
In
‐
line
Memory
Modules
(RDIMM)
and
Load
Reduced
Dual
In
‐
line
Memory
Modules
(LRDIMM)
•
Non
‐
volatile
on
‐
board
memory
‐
Flash
memory
devices.
•
Optional
on
‐
board
user
memory
‐
One
or
two
eUSB
Flash
modules.
•
Mass
storage
‐
One
or
two
1.8”
SSD
modules
and
any
RTM
hard
disk
drives
(HDDs).
The
following
sections
provide
more
detailed
information.
Table 7. PCI Express Port Mapping
CPU
Port#
Port Width
PCI Express Peripheral
CPU0
PE1(A,B)
x8
Fabric Ethernet Controller
CPU0
PE3(A,B,C,D)
x16
MXM
CPU0
DMI2
x4
Patsburg DMI2 interface
CPU1
PE1A
x4
I350 Base/Front/RTM GbE controller
CPU1
PE1B
x4
Update Channel
CPU1
PE3A*
x4
RTM PCI Express port 0
CPU1
PE3B*
x4
RTM PCI Express port 1
CPU1
PE3CD*
x8
RTM PCI Express port 2
*
Note
: As with the CPU0 mapping, CPU1 Ports PE3(A,B,C,D) can alternately be combined to form a single x16
interface.
