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Wi-Fi&BT Module Series

AF50T Hardware Design

AF50T_Hardware_Design 52 / 52

LTE

Long Term Evolution

Mbps

Megabits per second

MCS

Modulation and Coding Scheme

MOQ

Minimum Order Quantity

PCB

Printed Circuit Board

PCM

Pulse Code Modulation

QAM

Quadrature Amplitude Modulation

QPSK

Quadrature Phase Shift Keying

Radio Frequency

Relative Humidity

RoHS

Restriction of Hazardous Substances

RTS

Request To Send

Receive

SDIO

Secure Digital Input/Output

TBD

To Be Determined

Transmit

UART

Universal Asynchronous Receiver/Transmitter

USB

Universal Serial Bus

VHT

Very High Throughput

max

Maximum Input High Level Voltage Value

min

Minimum Input High Level Voltage Value

max

Maximum Input Low Level Voltage Value

min

Minimum Input Low Level Voltage Value

max

Maximum Output Low Level Voltage Value

min

Minimum Output High Level Voltage Value

Summary of Contents for AF50T

Page 1: ...AF50T Hardware Design Wi Fi BT Module Series Version 1 0 1 Date 2020 12 17 Status Preliminary www quectel com ...

Page 2: ... notice Disclaimer While Quectel has made efforts to ensure that the functions and features under development are free from errors it is possible that these functions and features could contain errors inaccuracies and omissions Unless otherwise provided by valid agreement Quectel makes no warranties of any kind implied or express with respect to the use of features and functions under development ...

Page 3: ...ss solutions co ltd Transmitting reproducing disseminating and editing this document as well as using the content without permission are forbidden Offenders will be held liable for payment of damages All rights are reserved in the event of a patent grant or registration of a utility model or design Copyright Quectel Wireless Solutions Co Ltd 2020 All rights reserved ...

Page 4: ...es Table 1 2 Changed the name of pin 48 pin 60 pin 61 pin 3 pin 21 and pin 65 to RESERVED pin 22 from BT_DBG_RXD to BT_WAKEUP_HOST pin 23 from BT_DBG_TXD to HOST_WAKEUP_BT 3 Updated the pin description Table 3 4 Updated the recommended operating power supply range Table 4 and Table 19 5 Deleted Chapter 3 5 3 6 Updated the reference circuit for RF antenna interfaces Figure 12 7 Added data of curren...

Page 5: ...EN 21 3 5 2 PCIe Interface 21 3 6 BT Interface 22 3 6 1 BT_EN 23 3 6 2 PCM Interface 23 3 6 3 UART Interface 24 3 7 Control Signal Pins 25 3 7 1 SW_CTRL 25 3 7 2 HOST_WAKEUP_BT and BT_WAKEUP_HOST 25 3 8 Coexistence Interfaces 26 3 8 1 UART Coexistence Interface 26 3 8 2 Other Coexistence Interfaces 27 3 9 WLAN_SLP_CLK Interface 27 3 10 RF Antenna Interfaces 28 3 10 1 Operating Frequency 28 3 10 2 ...

Page 6: ... 5 1 Conducted RF Performance of Wi Fi 37 4 5 2 Conducted RF Performance of Bluetooth 41 4 6 Electrostatic Discharge 42 5 Mechanical Dimensions 43 5 1 Mechanical Dimensions of the Module 43 5 2 Recommended Footprint 45 5 3 Top and Bottom Views of the Module 46 6 Storage Manufacturing and Packaging 47 6 1 Storage 47 6 2 Manufacturing and Soldering 48 6 3 Packaging 49 7 Appendix A References 51 ...

Page 7: ...tion of RF Antenna Interfaces 28 Table 16 Operating Frequency of the Module 28 Table 17 Antenna Cable Requirements 31 Table 18 Antenna Requirements 31 Table 19 Absolute Maximum Ratings 34 Table 20 Recommended Operating Conditions 35 Table 21 General DC Electrical Characteristics 35 Table 22 Current Consumption of the Module Normal Operation 36 Table 23 Conducted RF Output Power at 2 4 GHz SISO 37 ...

Page 8: ...on 26 Figure 12 Reference Circuit for RF Antenna Interfaces 29 Figure 13 Microstrip Design on a 2 layer PCB 29 Figure 14 Coplanar Waveguide Design on a 2 layer PCB 29 Figure 15 Coplanar Waveguide Design on a 4 layer PCB Layer 3 as Reference Ground 30 Figure 16 Coplanar Waveguide Design on a 4 layer PCB Layer 4 as Reference Ground 30 Figure 17 Dimensions of the U FL R SMT Connector Unit mm 32 Figur...

Page 9: ...face and hardware interfaces which are connected with customers applications The document helps customers quickly understand module interface specifications as well as the electrical and mechanical details Associated with application notes and user guides customers can use AF50T module to design and set up automotive industry mobile applications easily ...

Page 10: ... cause interference on sensitive medical equipment so please be aware of the restrictions on the use of wireless devices when in hospitals clinics or other healthcare facilities Cellular terminals or mobiles operating over radio signal and cellular network cannot be guaranteed to connect in certain conditions such as when the mobile bill is unpaid or the U SIM card is invalid When emergency help i...

Page 11: ...s LTE WLAN BT coexistence interface It is designed to be used in conjunction with Quectel 5G V2X module AG55xQ series to provide it with WLAN and BT functions 2 2 Key Features The following table describes the key features of AF50T module Table 1 Key Features Features Details Power Supply Core supply voltage 0 95 V 1 35 V 1 9 V I O supply voltage 1 8 V RF supply voltage 3 85 V Operating Frequency ...

Page 12: ...HT80 MCS9 13 dBm 802 11ax HE20 MCS11 12 dBm 802 11ax HE40 MCS11 12 dBm 802 11ax HE80 MCS11 12 dBm Protocol Features IEEE 802 11 a b g n ac ax Bluetooth 5 1 Operation Mode AP STA Modulation CCK BPSK QPSK 16QAM 64QAM 256QAM 1024QAM WLAN Interface PCIe BT Interface UART and PCM Antenna Interface Wi Fi BT antenna interface 50 Ω impedance Physical Characteristics Size 19 5 0 2 mm 21 5 0 2 mm 2 3 0 2 mm...

Page 13: ...odule Figure 1 Functional Diagram of AF50T Module 2 4 Evaluation Board To help customers develop applications with AF50T module conveniently Quectel supplies the evaluation board EVB USB to RS232 converter cable USB data cable power adapter antenna and other peripherals to control or test the module For more details see document 1 and or document 2 ...

Page 14: ...ule is equipped with 108 LGA pins that can be connected to the cellular application platform The subsequent chapters will provide a detailed introduction to the following interfaces and pins of the module Power supply WLAN interface BT interface Control signal pins Coexistence interfaces WLAN_SLP_CLK interface RF antenna interfaces ...

Page 15: ...ERVED 64 RESERVED 63 VDD_RF 62 RESERVED 61 RESERVED 60 RESERVED 59 COEX_TXD 58 RESERVED 57 SW_CTRL 107 GND 36 PCM_DOUT 37 PCM_CLK 38 BT_CTS 39 BT_TXD 40 RESERVED 41 LAA_TXEN 42 WLAN_TXE N 43 VDD_IO 44 GND 45 VDD_CORE _VM 46 VDD_CORE _VH 35 PCM_SYNC 76 PCM_DIN 77 BT_RTS 78 BT_RXD 79 RESERVED 80 PA_MUTE 81 LAA_RX 82 LAA_AS_EN 83 BT_EN 84 WLAN_EN 108 GND 86 GND 87 GND 88 GND 98 GND 99 GND 100 GND 89 ...

Page 16: ... It must be provided with sufficient current up to 1 7 A VDD_CORE_ VM 45 PI Voltage for core mid voltage Vmin 1 28 V Vnorm 1 35 V Vmax 1 42 V It must be provided with sufficient current up to 0 4 A VDD_CORE_ VH 46 PI Voltage for core high voltage Vmin 1 85 V Vnorm 1 9 V Vmax 2 0 V It must be provided with sufficient current up to 0 4 A VDD_IO 43 PI Power supply for the module s I O pins Vmin 1 71 ...

Page 17: ...X_M 11 AI PCIe receive PCIE_ CLKREQ_N 12 DO PCIe clock request VOLmax 0 45 V VOHmin 1 35 V 1 8 V power domain PCIE_RST_N 14 DI PCIe reset VILmin 0 3 V VILmax 0 63 V VIHmin 1 17 V VIHmax 2 1 V 1 8 V power domain PCIE_ WAKE_N 13 DO PCIe wakes up host VOLmax 0 45 V VOHmin 1 35 V 1 8 V power domain BT Interface Pin Name Pin No I O Description DC Characteristics Comment BT_EN 83 DI BT enable control VI...

Page 18: ...nal Pins Pin Name Pin No I O Description DC Characteristics Comment SW_CTRL 57 DO Control PMIC outputs VOLmax 0 45 V VOHmin 1 35 V 1 8 V power domain HOST_ WAKEUP_ 23 DI Host wakes up BT VILmin 0 3 V VILmax 0 63 V VIHmin 1 17 V VIHmax 2 1 V 1 8 V power domain If unused keep this pin open BT_WAKEUP_ HOST 22 DO BT wakes up the host VOLmax 0 45 V VOHmin 1 35 V 1 8 V power domain If unused keep this p...

Page 19: ...open PA_MUTE 80 DI WLAN XFEM control to disable WLAN PA VILmin 0 3 V VILmax 0 63 V VIHmin 1 17 V VIHmax 2 1 V 1 8 V power domain If unused keep this pin open RF Antenna Interfaces Pin Name Pin No I O Description DC Characteristics Comment ANT_WIFI0 28 IO BT and 2 4 5 GHz WLAN antenna interface 0 50 Ω impedance ANT_WIFI1 33 IO 2 4 5 GHz WLAN antenna interface 1 50 Ω impedance ANT_BT 25 IO Reserved ...

Page 20: ...uit for VDD_CORE_VL VDD_CORE_VM VDD_CORE_VH and VDD_IO 1 Please keep all RESERVED and unused pins open 2 means under development Pin Name Pin No Description Min Typ Max Unit VDD_ CORE_VL 1 2 47 Voltage for core low voltage 0 9 0 95 1 05 V VDD_ CORE_VM 45 Voltage for core mid voltage 1 28 1 35 1 42 V VDD_ CORE_VH 46 Voltage for core high voltage 1 85 1 9 2 0 V VDD_IO 43 Power supply for the module ...

Page 21: ...ng figure shows a reference design for VDD_RF which is controlled by WLAN_PWR_EN1 of AG55xQ series WLAN_PWR_EN1 of TPS62130A Q1 should be connected to the pin 222 WLAN_PWR_EN1 of AG55xQ series module For more details see document 3 Figure 4 Reference Circuit for VDD_RF 3 5 WLAN Interface The following figure shows the WLAN interface connection between AF50T and AG55xQ series modules Figure 5 WLAN ...

Page 22: ...F50T Table 6 Pin Definition of PCIe Interface The following figure shows the PCIe interface connection between AF50T and AG55xQ series modules Pin Name Pin No I O Description Comment WLAN_EN 84 DI WLAN function enable control Active high Pin Name Pin No I O Description Comment PCIE_REFCLK_P 54 AI PCIe reference clock Require differential impedance of 85 Ω PCIE_REFCLK_M 9 AI PCIe reference clock PC...

Page 23: ...tal grounding And the differential impedance is 85 Ω 10 For PCIe signal traces the maximum length of each differential data pair TX RX REFCLK is recommended to be less than 300 mm and each differential data pair matching should be less than 0 7 mm 5 ps Spacing to all other signals inter interface is four times of trace width Do not route signal traces under crystals oscillators magnetic devices or...

Page 24: ...evel Table 7 Pin Definition of BT_EN Pin Name Pin No I O Description Comment BT_EN 83 DI BT enable control Active high 3 6 2 PCM Interface The following table shows the pin definition of PCM interface Table 8 Pin Definition of PCM Interface Pin Name Pin No I O Description Comment PCM_DIN 76 DI PCM data input 1 8 V power domain PCM_SYNC 35 DI PCM data frame sync 1 8 V power domain PCM_CLK 37 DI PCM...

Page 25: ...on of UART interface Table 9 Pin Definition of UART Interface Pin Name Pin No I O Description Comment BT_RTS 77 DO BT UART request to send 1 8 V power domain BT_CTS 38 DI BT UART clear to send 1 8 V power domain BT_TXD 39 DO BT UART transmit 1 8 V power domain BT_RXD 78 DI BT UART receive 1 8 V power domain The following figure shows the reference design for UART interface connection between AF50T...

Page 26: ...lowing table shows the pin definition of SW_CTRL Table 10 Pin Definition of SW_CTRL The following figure shows the reference design for SW_CTRL connection between AF50T and AG55xQ series modules Figure 10 SW_CTRL Connection 3 7 2 HOST_WAKEUP_BT and BT_WAKEUP_HOST The following table shows the pin definition of HOST_WAKEUP_BT and BT_WAKEUP_HOST Pin Name Pin No I O Description Comment SW_CTRL 57 DO ...

Page 27: ...evelopment means under development 3 8 Coexistence Interfaces 3 8 1 UART Coexistence Interface The following table shows the pin definition of UART coexistence interface Table 12 Pin Definition of UART Coexistence Interface Pin Name Pin No I O Description Comment COEX_TXD 59 DO LTE WLAN BT coexistence transmit If unused keep this pin open COEX_RXD 16 DI LTE WLAN BT coexistence receive If unused ke...

Page 28: ...le If unused keep this pin open LAA_RX 81 DI WLAN XFEM control for LAA receiver If unused keep this pin open WLAN_TXEN 42 DO WLAN XFEM control for WLAN TX enable If unused keep this pin open PA_MUTE 80 DI WLAN XFEM control to disable WLAN PA If unused keep this pin open means under development 3 9 WLAN_SLP_CLK Interface An external 32 768 kHz sleep clock connecting to WLAN_SLP_CLK is necessary AF5...

Page 29: ...e 16 Operating Frequency of the Module Feature Frequency Unit 2 4 GHz WLAN 2 412 2 472 GHz 5 GHz WLAN 5 180 5 825 GHz BT 2 402 2 480 GHz 3 10 2 Reference Design of RF Antenna Interfaces AF50T module provides three RF antenna interfaces for antenna connection A reference circuit design for an RF antenna interface is shown below It is recommended to reserve a π type and LCs matching circuit for bett...

Page 30: ...s is usually determined by the trace width W the materials dielectric constant the height from the reference ground to the signal layer H and the spacing between RF traces and grounds S Microstrip or coplanar waveguide is typically used in RF layout to control characteristic impedance The following are reference designs of microstrip or coplanar waveguide with different PCB structures Figure 13 Mi...

Page 31: ...lly connected to ground The distance between the RF pins and the RF connector should be as short as possible and all the right angle traces should be changed to curved ones The recommended trace angle is 135 There should be clearance under the signal pin of the antenna connector or solder joint The reference ground of RF traces should be complete Meanwhile adding some ground vias around RF traces ...

Page 32: ...les and antennas Table 17 Antenna Cable Requirements Type Requirements 2 412 2 472 GHz Cable insertion loss 1 dB 5 180 5 825 GHz Cable insertion loss 1 dB Table 18 Antenna Requirements Type Requirements Frequency Range 2 412 2 472 GHz 5 180 5 825 GHz VSWR 2 1 recommended Gain dBi Typical 3 Max Input Power W 50 Input Impedance Ω 50 Polarization Type Vertical ...

Page 33: ...allation If RF connector is used for antenna connection it is recommended to use U FL R SMT connector provided by Hirose Figure 17 Dimensions of the U FL R SMT Connector Unit mm U FL LP serial connectors listed in the following figure can be used to match the U FL R SMT Figure 18 Mechanicals of UF L LP Connectors Unit mm ...

Page 34: ...ies AF50T Hardware Design AF50T_Hardware_Design 33 52 The following figure describes the space factor of mated connector Figure 19 Space Factor of Mated Connector Unit mm For more details please visit http www hirose com ...

Page 35: ...etails are listed in the subsequent chapters 4 2 Electrical Characteristics The following table shows the absolute maximum ratings Table 19 Absolute Maximum Ratings Parameter Min Max Unit VDD_CORE_VL 0 3 VDDX 0 2 V VDD_CORE_VM 0 3 VDDX 0 2 V VDD_CORE_VH 0 3 VDDX 0 2 V VDD_IO 0 3 VDDX 0 2 V VDD_RF 3 0 4 8 V Digital I O Input Voltage 0 3 VDD_IO 0 2 V VDDX is the supply voltage associated with the in...

Page 36: ...IO 1 71 1 8 1 89 V VDD_RF 3 3 3 85 4 25 V 4 3 I O Interface Characteristics The following table shows the general DC electrical characteristics over recommended operating conditions unless otherwise specified Table 21 General DC Electrical Characteristics Symbol Parameter Min Max Unit VIH High Level Input Voltage 0 65 VDD_IO VDD_IO 0 3 V VIL Low Level Input Voltage 0 3 0 35 VDD_IO V VOH High Level...

Page 37: ...m 231 78 108 56 69 23 3 54 271 37 mA TX HT40 MCS7 16 dBm 231 08 108 32 68 80 3 57 238 83 mA 802 11a 5 GHz TX 6 Mbps 17 dBm 229 91 126 78 69 15 3 79 252 32 mA TX 54 Mbps 15 dBm 224 22 122 03 66 44 3 75 198 96 mA 802 11n 5 GHz TX HT20 MCS0 17 dBm 217 62 129 90 69 17 3 79 251 08 mA TX HT20 MCS7 15 dBm 219 53 126 77 68 88 3 79 224 83 mA TX HT40 MCS0 17 dBm 234 52 126 83 69 18 3 79 254 55 mA TX HT40 MC...

Page 38: ... 11n HT20 MCS7 14 16 18 dBm 802 11n HT40 MCS0 17 19 21 dBm 802 11n HT40 MCS7 14 16 18 dBm 802 11ax HE20 MCS0 17 19 21 dBm 2 4 GHz TX HE20 MCS11 14 dBm 222 32 131 51 68 60 3 57 222 00 mA TX HE40 MCS0 19 dBm 237 86 133 69 69 10 3 58 269 26 mA TX HE40 MCS11 14 dBm 238 90 133 92 68 70 3 58 224 56 mA 802 11ax 5 GHz TX HE20 MCS0 17 dBm 235 56 138 64 77 94 3 78 251 82 mA TX HE20 MCS11 12 dBm 234 59 138 5...

Page 39: ...02 11n HT40 MCS0 20 22 24 dBm 802 11n HT40 MCS7 17 19 21 dBm 802 11ax HE20 MCS0 20 22 24 dBm 802 11ax HE20 MCS11 15 17 19 dBm 802 11ax HE40 MCS0 20 22 24 dBm 802 11ax HE40 MCS11 15 17 19 dBm Table 25 Conducted RF Output Power at 5 GHz SISO Frequency Min Typ Max Unit 802 11a 6 Mbps 15 17 19 dBm 802 11a 54 Mbps 13 15 17 dBm 802 11n HT20 MCS0 15 17 19 dBm 802 11n HT20 MCS7 13 15 17 dBm 802 11n HT40 M...

Page 40: ... dBm 802 11ax HE80 MCS0 15 17 19 dBm 802 11ax HE80 MCS11 10 12 14 dBm Table 26 Conducted RF Output Power at 5 GHz MIMO Frequency Min Typ Max Unit 802 11n HT20 MCS0 18 20 22 dBm 802 11n HT20 MCS7 16 18 20 dBm 802 11n HT40 MCS0 18 20 22 dBm 802 11n HT40 MCS7 16 18 20 dBm 802 11ac VHT20 MCS0 18 20 22 dBm 802 11ac VHT20 MCS8 15 17 19 dBm 802 11ac VHT40 MCS0 18 20 22 dBm 802 11ac VHT40 MCS9 14 16 18 dB...

Page 41: ...ving Sensitivity Typ 802 11b 1 Mbps 96 dBm 802 11b 11 Mbps 87 dBm 802 11g 6 Mbps 92 dBm 802 11g 54 Mbps 74 dBm 802 11n HT20 MCS0 92 dBm 802 11n HT20 MCS7 73 dBm 802 11n HT40 MCS0 89 dBm 802 11n HT40 MCS7 71 dBm 802 11ax HE20 MCS0 92 dBm 802 11ax HE20 MCS11 62 dBm 802 11ax HE40 MCS0 89 dBm 802 11ax HE40 MCS11 60 dBm Table 28 Conducted RF Receiving Sensitivity at 5 GHz Frequency Receiving Sensitivit...

Page 42: ... VHT80 MCS0 87 dBm 802 11ac VHT80 MCS9 62 dBm 802 11ax HE20 MCS0 93 dBm 802 11ax HE20 MCS11 63 dBm 802 11ax HE40 MCS0 90 dBm 802 11ax HE40 MCS11 60 dBm 802 11ax HE80 MCS0 87 dBm 802 11ax HE80 MCS11 56 dBm 4 5 2 Conducted RF Performance of Bluetooth Table 29 Conducted RF Performance of Bluetooth Frequency Transmitting Power Typ Transmitting Power Max Receiving Sensitivity Typ Unit BR 8 10 93 dBm ED...

Page 43: ... apply to ESD sensitive components Proper ESD handling and packaging procedures must be applied throughout the processing handling and operation of any application that incorporates the module The following table shows the module electrostatic discharge characteristics Table 30 Electrostatic Discharge Characteristics Tested Interfaces Contact Discharge Air Discharge Unit VDD GND 5 10 kV All Antenn...

Page 44: ...chanical Dimensions This chapter describes the mechanical dimensions of AF50T module All dimensions are measured in millimeter mm and the dimensional tolerances are 0 05 mm unless otherwise specified 5 1 Mechanical Dimensions of the Module Figure 20 AF50T Top and Side Dimensions ...

Page 45: ...Wi Fi BT Module Series AF50T Hardware Design AF50T_Hardware_Design 44 52 Figure 21 AF50T Bottom Dimension Bottom View The package warpage level of the module conforms to JEITA ED 7306 standard NOTE ...

Page 46: ...50T_Hardware_Design 45 52 5 2 Recommended Footprint Figure 22 Recommended Footprint Bottom View 1 For easy maintenance of the module please keep about 3mm spaces between the module and other components on host PCB 2 Keep all RESERVED pins open NOTES ...

Page 47: ... Top and Bottom Views of the Module Figure 23 Top View of the Module Figure 24 Bottom View of the Module Images above are for illustration purpose only and may differ from the actual module For authentic appearance and label please refer to the module received from Quectel NOTE ...

Page 48: ...module must be processed in reflow soldering or other high temperature operations within 168 hours Otherwise the module should be stored in an environment where the relative humidity is less than 10 e g a drying cabinet 4 The module should be pre baked to avoid blistering cracks and inner layer separation in PCB under the following circumstances The module is not stored in Recommended Storage Cond...

Page 49: ... the squeegee to apply the solder paste on the surface of stencil thus making the paste fill the stencil openings and then penetrate to the PCB The force on the squeegee should be adjusted properly to produce a clean stencil surface on a single pass To ensure the module soldering quality the thickness of stencil for the module is recommended to be 0 13 0 15 mm For more details see document 5 It is...

Page 50: ... still clearly identifiable and the QR code is still readable although white rust may be found 3 If a conformal coating is necessary for the module do NOT use any coating material that may chemically react with the PCB or shielding cover and prevent the coating material from flowing into the module 6 3 Packaging AF50T module is packaged in a vacuum sealed bag which is ESD protected The bag should ...

Page 51: ... Module Series AF50T Hardware Design AF50T_Hardware_Design 50 52 Table 32 Reel Packaging Model Name MOQ for MP Minimum Package TBD Minimum Package TBD AF50T TBD Size TBD N W TBD G W TBD Size TBD N W TBD G W TBD ...

Page 52: ..._QuecOpen_Reference_Design AG55xQ series reference design 4 Quectel_RF_Layout_Application_Note RF layout application note 5 Quectel_Module_Secondary_SMT_User_Guide Module secondary SMT user guide Table 34 Terms and Abbreviations Abbreviation Description AP Access Point BPSK Binary Phase Shift Keying BT Bluetooth CCK Complementary Code Keying CTS Clear To Send ESD Electrostatic Discharge GND Ground...

Page 53: ...Relative Humidity RoHS Restriction of Hazardous Substances RTS Request To Send RX Receive SDIO Secure Digital Input Output TBD To Be Determined TX Transmit UART Universal Asynchronous Receiver Transmitter USB Universal Serial Bus VHT Very High Throughput VIHmax Maximum Input High Level Voltage Value VIHmin Minimum Input High Level Voltage Value VILmax Maximum Input Low Level Voltage Value VILmin M...

Page 54: ...CC Part 2 1093 If the device is used for other equipment that separate approval is required for all other operating configurations including portable configurations with respect to 2 1093 and different antenna configurations For this device OEM integrators must be provided with labeling instructions of finished products Please refer to KDB784748 D01 v07 section 8 Page 6 7 last two paragraphs A cer...

Page 55: ...essly approved by the manufacturer could void the user s authority to operate the equipment To ensure compliance with all non transmitter functions the host manufacturer is responsible for ensuring compliance with the module s installed and fully operational For example if a host was previously authorized as an unintentional radiator under the Supplier s Declaration of Conformity procedure without...

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