Wi-Fi&BT Module Series
AF50T Hardware Design
AF50T_Hardware_Design 22 / 52
Figure 6: PCIe Interface Connection
To ensure the signal integrity of PCIe interface, C1 and C2 should be placed close to the AG55xQ series
module, and C3 and C4 should be placed close to the AF50T.
The extra stubs of traces must be as short
as possible.
The following principles of PCIe interface design should be complied with, so as to meet PCIe Gen2
specifications.
It is important to route the PCIe signal traces as differential pairs with total grounding. And the
differential impedance is 85 Ω ±10 %.
For PCIe signal traces, the maximum length of each differential data pair (TX/RX/REFCLK) is
recommended to be less than 300 mm, and each differential data pair matching should be less than
0.7 mm (5 ps).
Spacing to all other signals (inter-interface) is four times of trace width.
Do not route signal traces under crystals, oscillators, magnetic devices, or RF signal traces. It is
important to route the PCIe differential traces in inner-layer of the PCB and surround the traces with
ground on that layer and with ground planes above and below.
3.6. BT Interface
The following figure shows the block diagram of BT interface
connection between AF50T and AG55xQ
series modules.
