Quectel AF50T, Hardware Design, Page: 17 / 55

Wi-Fi&BT Module Series
AF50T Hardware Design
AF50T_Hardware_Design 16 / 52
WLAN Interface
Pin Name
Pin
No.
I/O Description DC Characteristics Comment
WLAN_EN 84 DI
WLAN function
enable control
V
IL
min = -0.3 V
V
IL
max = 0.63 V
V
IH
min = 1.17 V
V
IH
max = 2.1 V
1.8 V power domain.
Active high.
PCIE_
REFCLK_P
54 AI
PCIe reference clock
(+)
Require differential
impedance of 85 Ω.
PCIE_
REFCLK_M
9 AI
PCIe reference clock
(-)
PCIE_TX_P 52 AO PCIe transmit (+)
PCIE_TX_M 7 AO PCIe transmit (-)
PCIE_RX_P 56 AI PCIe receive (+)
PCIE_RX_M 11 AI PCIe receive (-)
PCIE_
CLKREQ_N
12 DO PCIe clock request
V
OL
max = 0.45 V
V
OH
min = 1.35 V
1.8 V power domain
PCIE_RST_N 14 DI PCIe reset
V
IL
min = -0.3 V
V
IL
max = 0.63 V
V
IH
min = 1.17 V
V
IH
max = 2.1 V
1.8 V power domain
PCIE_
WAKE_N
13 DO PCIe wakes up host
V
OL
max = 0.45 V
V
OH
min = 1.35 V
1.8 V power domain
BT Interface
Pin Name
Pin
No.
I/O Description DC Characteristics Comment
BT_EN 83 DI BT enable control
V
IL
min = -0.3 V
V
IL
max = 0.63 V
V
IH
min = 1.17 V
V
IH
max = 2.1 V
1.8 V power domain.
Active high.
PCM_DIN* 76 DI PCM data input
V
IL
min = -0.3 V
V
IL
max = 0.63 V
V
IH
min = 1.17 V
V
IH
max = 2.1 V
1.8 V power domain.
PCM_SYNC* 35 DI
PCM data frame
sync
V
IL
min = -0.3 V
V
IL
max = 0.63 V
V
IH
min = 1.17 V
V
IH
max = 2.1 V
1.8 V power domain.