PT AMC131, Hardware Manual

Page: 85 / 108

Custom Register Summary
85
Register 0
This register provides the custom address offset 0d, 0h.
Register 1
This register provides the custom address offset 1d, 1h.
Table 7-2: Custom Address Offset 0d, 0h - Bits
7 6 5 4 3 2 1 0
RO (0) RW (1) H RW (1) H RW (1) H RO (0) RO (0) RO (0) RO (0)
0 PHY1_
RST DDR2_
RST_D2 DDR2_
RST_D1 0 0 0 0
Table 7-3: Custom Address Offset 0d, 0h - Description
Name Description
DDR2_RST_D1 Writing:
• 1 to this bit activates the taller SO-CDIMM DDR2 memory module reset
• 0 to this bit deactivates this reset
DDR2_RST_D2 Writing:
• 1 to this bit activates the shorter SO-CDIMM DDR2 memory module reset
• 0 to this bit deactivates this reset
PHY1_RST Writing:
• 1 to this bit activates the on-board quad PHY reset
• 0 to this bit deactivates this reset
Table 7-4: Custom Address Offset 1d, 1h - Bits
7 6 5 4 3 2 1 0
RO (0) RO (0) RO (0) RO (0) RO (0) RO (0) RO (0) RO (0)
cpu_rio_id7 cpu_rio_id6 cpu_rio_id5 cpu_rio_small SW1 4:1
Table 7-5: Custom Address Offset 1d, 1h - Bits - Description
Name Description
SW1 4:1 Reads current switch settings for switch pack SW1
cpu_rio_small SRIO system addressing:
0 = Reflects the status of the SRIO port as a small system device (using 8-bit addressing).
1 = Large system device (16-bit addressing)
cpu_rio_id5 SRIO Small system device ID bit 5
cpu_rio_id6 SRIO Small system device ID bit 6
cpu_rio_id7 SRIO Small system device ID bit 7