BIOS Setup Information
PEB-2530VL User’s Manual
4-15
4.2.4
CHIPSET FEATURES SETUP
ADVANCED OPTIONS. The parameters in this screen are for system designers,
service personnel, and technically competent users only. Do not reset these values
unless you understand the consequences of your changes.
SDRAM CAS latency Time
When synchronous DRAM is installed, the number of clock cycles of CAS latency
depends on the DRAM timing. Do not reset this field from the default value
specified by the system designer.
The choice: Auto, 2T, 3T.
SDRAM Clock Ratio Div By
This item allows user to set the DRAM timing.
The choice: 3, 4.
16-bit I/O Recovery (CLK)
The I/O recovery mechanism adds bus clock cycles between PCI-originated I/O
cycles to the ISA bus. This delay takes place because the PCI bus is so much faster
than the ISA bus.
The choice: from 1 to 16 CPU clocks.
