PLDA XpressGX5LP-SE Reference Manual Download

Page: 28 / 36

Ch.3 XpressGX5LP-SE Features

XpressGX5LP-SE Reference Manual

ddr3_Bank0_d58

AG12

ddr3_Bank1_d58

D28

ddr3_Bank0_d59

AD12

ddr3_Bank1_d59

A28

ddr3_Bank0_d60

AF11

ddr3_Bank1_d60

F29

ddr3_Bank0_d61

AE10

ddr3_Bank1_d61

B29

ddr3_Bank0_d62

AL12

ddr3_Bank1_d62

B28

ddr3_Bank0_d63

AE12

ddr3_Bank1_d63

A29

ddr3_Bank0_d64

AV11

ddr3_Bank1_d64

G34

ddr3_Bank0_d65

AR11

ddr3_Bank1_d65

E32

ddr3_Bank0_d66

AK11

ddr3_Bank1_d66

H34

ddr3_Bank0_d67

AL11

ddr3_Bank1_d67

F32

ddr3_Bank0_d68

AW11

ddr3_Bank1_d68

K33

ddr3_Bank0_d69

AT11

ddr3_Bank1_d69

J34

ddr3_Bank0_d70

AR12

ddr3_Bank1_d70

J33

ddr3_Bank0_d71

AU11

ddr3_Bank1_d71

K34

ddr3_Bank0_dqs00n

AE15

ddr3_Bank1_dqs00n

E25

ddr3_Bank0_dqs00p

AD15

ddr3_Bank1_dqs00p

E24

ddr3_Bank0_dqs01n

AG18

ddr3_Bank1_dqs01n

R26

ddr3_Bank0_dqs01p

AF19

ddr3_Bank1_dqs01p

R25

ddr3_Bank0_dqs02n

AG10

ddr3_Bank1_dqs02n

F27

ddr3_Bank0_dqs02p

AF10

ddr3_Bank1_dqs02p

G27

ddr3_Bank0_dqs03n

AW10

ddr3_Bank1_dqs03n

T28

ddr3_Bank0_dqs03p

AV10

ddr3_Bank1_dqs03p

U28

ddr3_Bank0_dqs04n

AF14

ddr3_Bank1_dqs04n

C31

ddr3_Bank0_dqs04p

AE14

ddr3_Bank1_dqs04p

D31

ddr3_Bank0_dqs05n

AU14

ddr3_Bank1_dqs05n

N31

ddr3_Bank0_dqs05p

AT14

ddr3_Bank1_dqs05p

P31

ddr3_Bank0_dqs06n

AP15

ddr3_Bank1_dqs06n

T30

ddr3_Bank0_dqs06p

AN15

ddr3_Bank1_dqs06p

U30

ddr3_Bank0_dqs07n

AJ12

ddr3_Bank1_dqs07n

G29

ddr3_Bank0_dqs07p

AH12

ddr3_Bank1_dqs07p

H29

ddr3_Bank0_dqs08n

AU12

ddr3_Bank1_dqs08n

E33

ddr3_Bank0_dqs08p

AT12

ddr3_Bank1_dqs08p

F33

ddr3_Bank0_odt0

AN16

ddr3_Bank1_odt0

A22

ddr3_Bank0_odt1

AJ7

ddr3_Bank1_odt1

B22

Bank 0

Bank 1

FPGA Pin

Signal

FPGA Pin

Signal

Table 9: DDR3L SDRAM pin assignments

Summary of Contents for XpressGX5LP-SE

Page 1: ...Version 1 0 0 November 2013 Copyright PLDA 1996 2013 XpressGX5LP SE Reference Manual...

Page 2: ...in this document are given by PLDA in good faith This document is provided as is with no warranties whatsoever including any warranty of merchantability non infringement fitness for any particular pu...

Page 3: ...1 XpressGX5LP SE Layout 9 2 2 Block Diagram of the Board 10 2 3 Board Features 11 2 4 Mechanical Description 12 Chapter 3 XpressGX5LP SE Features 13 3 1 Stratix V GX FPGA Device 13 3 2 Board Configura...

Page 4: ...ssGX5LP SE clock assignments 19 Table 7 Pin assignments for the PCI Express endpoint connector 20 Table 8 QDR2 SRAM pin assignments 22 Table 9 DDR3L SDRAM pin assignments 25 Table 10 SFP pin assignmen...

Page 5: ...gure 5 Board configuration components 14 Figure 6 Max V 5M2210ZF256 board configuration and management module 14 Figure 7 PCI Express connector 20 Figure 8 QDR2 SRAM 22 Figure 9 DDR3L SDRAM 25 Figure...

Page 6: ...k and Contact Information Feedback about this document PLDA welcomes comments and suggestions about this documentation Please contact PLDA Technical Support and provide the following information the t...

Page 7: ...rotocols on fiber optic or copper tranceivers Stratix V GX FPGA 5SGXEA7K2F40C2N or 5SGXEA4K2F40C2N Board configuration module Power monitoring Power Up and reset controller IP protection PLDA Protocor...

Page 8: ...A detailed description of board features can be found in Section 2 3 1 3 System Requirements To use XpressGX5LP SE board features you must install the PLDA Software Tools The PLDA Software Tools can b...

Page 9: ...tes 3 0 V voltages These voltages are available on the mezzanine power supply daughter card which is mounted on the XpressGX5LP SE by default This daughter card is supplied with the XpressGX5LP SE boa...

Page 10: ...essGX5LP SE Architecture XpressGX5LP SE Reference Manual 10 2 2 Block Diagram of the Board The XpressGX5LP SE board is based on an Altera Stratix V GX FPGA as shown below Figure 2 XpressGX5LP SE block...

Page 11: ...es and an Altera MAX V The Flash devices can be programmed using PLDA s FlashPCI software Each device is directly connected to the FPGA and the CPLD pins Section 3 2 JTAG connector A mini JTAG connect...

Page 12: ...al Description The following diagram illustrates the mechanical architecture of the XpressGX5LP SE board without the fansink mounted Note The overall height of the board that is the height of the high...

Page 13: ...ssGX5LP SE features a mini JTAG connector A 10cm cable is provided with the board so you can configure the FPGA with your USB BLASTER and Quartus The cable must be plugged into the board as shown in t...

Page 14: ...re shows the configuration components of the XpressGX5LP SE Boot sector selection switch SW1 4 LEDs JTAG Conf RST Figure 5 Board configuration components The following diagram shows the board configur...

Page 15: ...13 flash_ad10 AU24 L4 flash2_oe AN28 A4 flash_data11 AW34 B13 flash_ad11 AW25 M2 flash2_rst AM28 C3 flash_data12 AV34 B11 flash_ad12 AP27 J2 flash2_wait AK27 B1 flash_data13 AW31 A15 flash_ad13 AU26 L...

Page 16: ...29 clrconfig E14 Reset push button BPCONF Max_SW0 C14 Configuration boot sector switch SW1 4 flash_reload_enable conf_rfu0 L14 Flash reload enable AV22 flash_boot_number conf_rfu1 N14 Flash boot numbe...

Page 17: ...roto_misc4 A6 fpga_proto_misc4 AC27 fpga_proto_misc5 B7 fpga_proto_misc5 AD26 proto_led0 M11 DSMAX3 LED Red proto_led1 M12 DSMAX4 LED Green proto_led2 M7 DSMAX5 LED Orange proto_led3 M6 DSMAX6 LED Gre...

Page 18: ...r User Sector SW1 4 1 64MB 7FF FFFF 400 0000 Sector 0 SW1 4 0 64MB 3FF FFFF 000 0000 CvP PR signals Configuration via protocol Partial reconfiguration Cvp_confdone M13 Cvp_confdone AT29 pr_done L12 pr...

Page 19: ...clock used for the Max V CPLDs Osc3 p n AK23 AL23 LVDS 125 MHz CLK used for PCIe Hard IP Osc4p n AE17 AE16 LVDS 100MHz CLK for global CLK network Osc5 p n E34 D34 LVDS 200 MHz CLK dedicated to DDR3L...

Page 20: ...mechanical Specification 2 0 and signals that appear bold are active signals implemented on the XpressGX5LP SE Side B Side A PCI Express Pin FPGA Pin Signal PCI Express Pin FPGA Pin Signal 1 12V 1 con...

Page 21: ...GND 29 AL36 mPETp3 30 RSVD 30 AL37 mPETn3 31 connected to mPRSNT 1 mPRSNT 2 31 GND 32 GND 32 RSVD 33 AH38 mPERp4 33 RSVD 34 AH39 mPERn4 34 GND 35 GND 35 AG36 mPETp4 36 GND 36 AG37 mPETn4 37 AF38 mPER...

Page 22: ...to mPRSNT 1 mPRSNT 2 48 AA37 mPETn7 49 GND 49 GND Bank 0 Bank 1 FPGA Pin Signal FPGA Pin Signal QDR2a_a00 U14 QDR2b_a00 T12 QDR2a_a01 P14 QDR2b_a01 K12 QDR2a_a02 J15 QDR2b_a02 K13 QDR2a_a03 T13 QDR2b_...

Page 23: ...9 QDR2a_bws1 K19 QDR2b_bws1 N8 QDR2a_CKn F18 QDR2b_CKn C9 QDR2a_CKp G18 QDR2b_CKp C8 QDR2a_CQn P16 QDR2b_CQn M11 QDR2a_CQp H16 QDR2b_CQp B10 QDR2a_d00 D18 QDR2b_d00 E9 QDR2a_d01 D19 QDR2b_d01 G10 QDR2...

Page 24: ...q05 C16 QDR2b_q05 H11 QDR2a_q06 D16 QDR2b_q06 J11 QDR2a_q07 F17 QDR2b_q07 K10 QDR2a_q08 G16 QDR2b_q08 N10 QDR2a_q09 U15 QDR2b_q09 U10 QDR2a_q10 T15 QDR2b_q10 U9 QDR2a_q11 T16 QDR2b_q11 R10 QDR2a_q12 R...

Page 25: ...ddr3_Bank1_a01 E20 ddr3_Bank0_a02 AF16 ddr3_Bank1_a02 E23 ddr3_Bank0_a03 AM16 ddr3_Bank1_a03 A23 ddr3_Bank0_a04 AR19 ddr3_Bank1_a04 G20 ddr3_Bank0_a05 AG16 ddr3_Bank1_a05 F23 ddr3_Bank0_a06 AP19 ddr3_...

Page 26: ...3_Bank0_d05 AG15 ddr3_Bank1_d05 F24 ddr3_Bank0_d06 AD16 ddr3_Bank1_d06 H25 ddr3_Bank0_d07 AC15 ddr3_Bank1_d07 G25 ddr3_Bank0_d08 AH19 ddr3_Bank1_d08 J25 ddr3_Bank0_d09 AJ18 ddr3_Bank1_d09 P26 ddr3_Ban...

Page 27: ...k1_d38 G30 ddr3_Bank0_d39 AC14 ddr3_Bank1_d39 C30 ddr3_Bank0_d40 AV14 ddr3_Bank1_d40 N30 ddr3_Bank0_d41 AP13 ddr3_Bank1_d41 L30 ddr3_Bank0_d42 AV13 ddr3_Bank1_d42 R31 ddr3_Bank0_d43 AN13 ddr3_Bank1_d4...

Page 28: ...s00p E24 ddr3_Bank0_dqs01n AG18 ddr3_Bank1_dqs01n R26 ddr3_Bank0_dqs01p AF19 ddr3_Bank1_dqs01p R25 ddr3_Bank0_dqs02n AG10 ddr3_Bank1_dqs02n F27 ddr3_Bank0_dqs02p AF10 ddr3_Bank1_dqs02p G27 ddr3_Bank0_...

Page 29: ...ank1_tdqs03n U27 ddr3_Bank0_tdqs03p AN10 ddr3_Bank1_tdqs03p U26 ddr3_Bank0_tdqs04n AG13 ddr3_Bank1_tdqs04n A31 ddr3_Bank0_tdqs04p AF13 ddr3_Bank1_tdqs04p B31 ddr3_Bank0_tdqs05n AP12 ddr3_Bank1_tdqs05n...

Page 30: ...two optical links Each transmitter can be driven by its SFPX_SUPPLY_EN active low control signal An SFPX_SUPPLY_FAULT fault signal is available in case of overload on transmitters Figure 10 QSFP inter...

Page 31: ...3_0 AG23 sfp0_gpio3_1 AT20 sfp1_gpio3_1 AG25 sfp0_mod_abs AH21 sfp1_mod_abs AJ24 sfp0_rx_los AP21 sfp1_rx_los AH25 sfp0_tx_disable AD20 sfp1_tx_disable AG22 sfp0_tx_fault AD21 sfp1_tx_fault AG21 sfp0_...

Page 32: ...lay SFP information and can also be used for user defined purposes Table 11 Dual tri color LED pin assignments LED SFP0_1 sfp0_led_g1 AW20 sfp0_led_r1 AU20 LED SFP0_2 sfp0_led_g2 AV20 sfp0_led_r2 AH27...

Page 33: ...he following table describes pin assignments for the LEDs Table 12 Pin assignments for the board LEDs Signal FPGA Pin LED Name LED Color user_led0 AJ20 DS2 Yellow user_led1 AK21 DS3 Yellow user_led2 A...

Page 34: ...e XpressGX5LP SE on SW1 These enable three IOs to be set to a logical 0 or a logical 1 A fourth switch SW1 4 enables you to select the configuration bit stream to load on the FPGA during configuration...

Page 35: ...he following table shows pin assignments for the EEPROMs Table 15 Pin assignments for the EEPROMs EEPROM 0 Signal FPGA Pin EEPROM 1Signal FPGA Pin eeprom0_scl J7 eeprom1_scl K6 eeprom0_sda K7 eeprom1_...

Page 36: ...1 8 V 2 5 V and 0 9 V voltages while the 3 3 V generates 3 0 V voltages as shown below Supply daughtercard 12 V 3 3 V Misc IOs 3 0V 2A 1 35V 16A VDD DDR3 1 5V for DDR3 0 9V 25A VCC_CORE VCC_HIP VCC_H...

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