17
XpressGX5LP-SE Reference Manual
Ch.3 XpressGX5LP-SE Features
por_VCCR_GXB
F14
VCCR_GXB Power on Reset
--
fpga_power_good
F15
FPGA power good
AC25
Protocore Dedicated Signals
prot0_out
G13
prot0_out
AG26
prot1_in0
E12
prot1_in0
AE25
prot1_in1
E13
prot1_in1
AF23
prot1_out
F12
prot1_out
AE24
prot2_in0
H13
prot2_in0
AG24
prot2_in1
G12
prot2_in1
AE23
prot2_out
F13
prot2_out
AJ26
fpga_proto_misc0
A5
fpga_proto_misc0
AB27
fpga_proto_misc1
A7
fpga_proto_misc1
AA26
fpga_proto_misc2
C7
fpga_proto_misc2
AC26
fpga_proto_misc3
B6
fpga_proto_misc3
AA27
fpga_proto_misc4
A6
fpga_proto_misc4
AC27
fpga_proto_misc5
B7
fpga_proto_misc5
AD26
proto_led0
M11
DSMAX3 LED (Red)
--
proto_led1
M12
DSMAX4 LED (Green)
--
proto_led2
M7
DSMAX5 LED (Orange)
--
proto_led3
M6
DSMAX6 LED (Green)
--
XpressGX5LP-SE Temp MGT
--
--
fpga_temp_n (LM83)
P5
--
--
fpga_temp_p (LM83)
R6
smb_temp_clk
N8
LM83 (U38.14)
--
smb_temp_d
P12
LM83 (U38.12)
--
temp_crit#
N9
LM83 (U38.16)
--
temp_int#
T12
LM83 (U38.11)
--
External Configuration Management Interface (on J3 Connector)
External_CPLD_IF_0
D13
TBD (pin J3.1]
--
External_CPLD_IF_1
D16
TBD (pin J3.3]
--
External_CPLD_IF_2
D14
TBD (pin J3.5]
--
External_CPLD_IF_3
E15
TBD (pin J3.7]
--
External_CPLD_IF_4
E16
TBD (pin J3.4]
--
External_CPLD_IF_5
D15
TBD (pin J3.6]
--
FPGA Configuration Signals
Signal
CPLD
Signal Name/Function
FPGA
Table 4: FPGA and CPLD pin assignments
