PDP-504CMX/1
172
1
2
3
4
1
2
3
4
C
D
F
A
B
E
Pin Function
No.
Pin Name
I/O
Pin Function
1
G
INA
/U
INA
I
Analog GINA or UINA signal input.
Sync signal is input on SYNCIN pin.
2
GSG1
I
GOUT/UOUT output buffer gain set input
3
G
INB
/U
INB
I
Analog GINB or UINB signal input.
Sync signal is input on SYNCIN pin.
4
(NC)
−
No connection
5
B
INA
/V
INA
I
Analog BINA or VINA signal input.
Sync signal is input on SYNCIN pin.
6
GSB1
I
BOUT/VOUT output buffer gain set input
7
B
INB
/V
INB
I
Analog BINB or VINB signal input.
Sync signal is input on SYNCIN pin.
8
(NC)
−
No connection
9
DISABLE
I
Power save function.
Built-in pull-down resistor.
L : Enable
H : Disable
(Output pins: ROUT/YOUT, GOUT/UOUT, and BOUT/VOUT are high impedance.)
10
GND3
−
Analog ground
11
B
OUT
/V
OUT
O
B/V signal output
12
VCC3
−
Analog 5V supply
13
GND2
−
Analog ground
14
G
OUT
/U
OUT
O
G/U signal output
15
VCC2
−
Analog 5V supply
16
GND1
−
Analog ground
17
R
OUT
/Y
OUT
O
R/Y signal output
18
VCC1
−
Analog 5V supply
19
GND4
−
Analog ground
20
RFC
−
LPF (lowpass filter) cutoff frequency setting resistor connection
21
VFC
I
LPF (lowpass filter) cutoff frequency setting voltage input
22
MUXSEL
I
Input select signal.
Built-in pull-down resistor.
L : XINA pin select
H : XINB pin select
23
THROUGH
I
Filter through
Built-in pull-down resistor.
L : Filter function
H : Filter through (buffer only)
24
VCC4
−
Analog 5V supply
25
R
INA
/Y
INA
I
Analog RINA or YINA signal input.
Sync signal is input on SYNCIN pin.
26
GSR1
I
ROUT/YOUT output buffer gain set input
27
R
INB
/Y
INB
I
Analog RINB or YINB signal input.
Sync signal is input on SYNCIN pin.
28
(NC)
−
No connection
