PDP-504CMX/1
46
1
2
3
4
1
2
3
4
C
D
F
A
B
E
3.1.4 SIGNAL ROUTE
AN5870
75
Ω
SW
SII1161CTG100 (DVI)
DVI RECEIVER
PD6435A IC5701
AN5870
75
Ω
SW
Differential
SW
BA7657
IC6001
CXA3516AR
IC6255
PD0278A
ANALOG
SLOT
SINGLE
R, G, B X 8bit X 2
DIGITAL
TC74HC126
SDRAM 16M
D-SUB
INPUT 1
OUTPUT
D-SUB
INPUT 2
DVI
INPUT 3
S
INPUT 4
BNC
or
RCA
OUTPUT
BNC
or
RCA
INPUT 5
BNC
×
5
or
RCA
×
3
C
Y
IC6107
PD0278A
V
SDRAM
64M
×
2
FLASH
ROM
32M
Y
X
2 Divide
SW
PD6435A IC5801
Y
X
2 Divide
SW
74VHC125
SM5301BS
LPF
SM5301BS
LPF
A/D PLL
BA7078AF
COMPOSITE
SYNC
COMPOSITE
SYNC
G ON SYNC
G ON SYNC
H, V
74HC125
74VHC125
5
→
3.3V
5
→
3.3V
SYNC SEP.
BA7078
SYNC SEP.
IC6002
AD9883AKST
A/D PLL
2
1
2
1
SYNC PROCESS
SYNC PROCESS
MANTA
VIDEO
PROCESS
MULTI
PROCESS
IP
IP
FRC
NR
LVDS
Sequence
IC7004
PE5362A
48bit DUAL: R, G, B X 8bit X2 H, V, CLK, DE
ANALOG
SYNC
IC7101
PD5855A
WIRED OR
IC5401
PEG054A-K
AN5870
75
Ω
SW
• Block Diagram