PDP-504CMX/1
168
1
2
3
4
1
2
3
4
C
D
F
A
B
E
MIDSCV
HSOUT
VSOUT
SOGOUT
REF
CLAMP
A/D
CLAMP
8
A/D
CLAMP
A/D
54
67
66
64
65
58
37
48
43
56
57
55
30
29
38
33
REF BYPASS
DATACK
BOUTA
GOUTA
ROUTA
SYNC
PROCESSING
AND CLOCK
GENERATION
SERIAL REGISTER
AND
POWER MANAGEMENT
RAIN
GAIN
BAIN
HSYNC
COAST
CLAMP
FILT
SCL
SDA
A0
12-19
8
2-9
8
70-77
GND
GREEN <7>
GREEN <6>
GREEN <5>
GREEN <4>
GREEN <3>
GREEN <2>
GREEN <1>
GREEN <0>
GND
BLUE <7>
BLUE <6>
BLUE <5>
BLUE <4>
BLUE <3>
BLUE <2>
BLUE <1>
BLUE <0>
GND
GND
GND
GND
GND
GND
GND
VD
VD
VD
VD
VD
VD
SDA
SCL
A0
RAIN
GAIN
BAIN
SOGIN
80 79 78 77 76
71 70 69 68 67 66 65
75 74 73 72
64 63 62 61
1
2
3
4
5
6
7
8
9
10
11
13
14
15
16
12
17
18
20
19
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
PIN 1
IDENTIFIER
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
GND
RED <0>
RED <1>
RED <2>
RED <3>
RED <4>
RED <5>
RED <6>
RED <7>
VDD
VDD
VDD
GND
HSOUT
SOGOUT
GND
GND
VSOUT
GND
GND
GND
GND
MIDSCV
CLAMP
GND
HSYNC
VSYNC
GND
GND
VDD
VDD
VDD
PVD
PVD
PVD
PVD
VD
VD
COAST
FILT
REF BYPASS
DATACK
AD9883AKST-110 (RGB ASSY : IC6602)
• 110 MSPS Analog Interface
Pin Arrangement (Top View)
Block Diagram
