DV-59AVi
154
1
2
3
4
1
2
3
4
C
D
F
A
B
E
Pin Name
Pin No
I/O
Description
Phase Lock Loops Pins
DIV_VCO
7
O
Output for External Phase Detector. This signal is the divided
VCO_CLK. It used by the external phase detector to compare
with the REF_SYT signal. The divide ratios are setup in CFR.
PFD
8
O
Output from Internal Phase Detector. This signal can feed
directly into the LPF and VCO if the internal phase detector is
used.
REF_SYT
6
O
Output for External Phase Detector. This signal represents
the SYT match for received audio or DV packets. The phase
detector uses it as input to detect differences between the
SYT match and the VCO clock.
VCO_CLK
5
I
Input from VCO. This is used to generate internal audio and
DV clocks for receive clock recovery.
Audio Frequency: 33.868MHz or 36.864MHz.
DV Frequency: 30.72MHz
Test Mode Pins
TEST_MODE0
2
I/O
Test Mode. Used for Internal TI testing. Should be tied low
for normal operation.
TEST_MODE1
3
I/O
Test Mode. Used for Internal TI testing. Should be tied low
for normal operation.
TEST_MODE2
TEST_MODE3
57
58
I/O
Test Mode. Used for Internal TI testing. Should be tied low
for normal operation.
