DV-59AVi
148
1
2
3
4
1
2
3
4
C
D
F
A
B
E
Pin Name
I/O
Description
GPIO8
71
I/O
GPIO8. Can be programmed as general-purpose input,
general-purpose output, or specific function. Power-up default
is input.
GPIO9
72
I/O
GPIO9. Can be programmed as general-purpose input,
general-purpose output, or specific function. Power-up default
is input.
GPIO10
87
I/O
GPIO10. Can be programmed as general-purpose input,
general-purpose output, or specific function. Power-up default
is input.
Physical Layer Pins
TPA0_N
TPA1_N
TPA2_N
TPA0_P
TPA1_P
TPA2_P
29
36
42
30
37
43
I/O
Twisted Pair A Differential Signal Terminals. For an unused
port, TPAN and TPAP signals can be left open.
TPB0_N
TPB1_N
TPB2_N
TPB0_P
TPB1_P
TPB2_P
25
33
39
26
34
40
I/O
Twisted Pair B Differential Signal Terminals. For an unused
port, TPBN and TPBP signals can be left open.
TPBIAS0
TPBIAS1
TPBIAS2
31
38
44
I/O
Twisted Pair Bias Output. These signals provide the 1.86V
nominal bias voltage needed for proper operation of the
twisted pair driver and receivers for signaling an ìactive
connectionî to a remote node.
For an unused port, TPBIAS can be left unconnected.
R1
R0
46
47
-
Current Setting Resistors. These pins are connected to
external resistors to set the internal operating currents and
cable driver output currents. A resistance of 6.34k
Ω
±
1% is
required to meet the IEEE 1394-1995 output voltage limits.
FILTER0
FILTER1
49
50
I/O
PLL Filter Terminals. These terminals are connected to an
external capacitor to form a lag-lead filter required for stable
operation of the internal frequency-multiplier PLL, which is
using the crystal oscillator. A 0.1
µ
F
±
10% capacitor is the
only external component required to complete this filter.
XI
X0
52
53
-
Crystal Oscillator Inputs. These terminals connect to a 24.576
MHz parallel resonant fundamental mode crystal. The
optimum values for the external shunt capacitors are
dependent on the crystal used.
CPS
21
I
Cable Power Status. Input to iceLynx-Micro used to detect if
cable power is present. This pin should be connected to the
cable power through 390 k
Ω
resistor.
MSPCTL
19
I
LINKON
61
O
Link On output. This signal is asserted whenever LPS is low
and a Link On packet is received from the 1394 bus.
High Speed Data Interface (HSDI) Port 0 Pins
HSDI_60958_IN
173
I
60958 Data Input.