DV-59AVi
143
5
6
7
8
5
6
7
8
C
D
F
A
B
E
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Pin Function
Pin Name
Pin No
I/O
Description
Power & Ground Pins
DISABLE_IFZ
64
I
Interface Disable. When asserted, the interfaces are put into
a Hi-Z state. Interfaces include: ex-CPU, HSDI, GPIO, and
WTCH_DG_TMRZ.
HPS
62
I
Host Power Status. This indicates the power status of the
external system to iceLynx-Micro. A rising edge indicates the
system CPU has been turned ON. (The internal ARM should
wake up.) A falling edge indicates the system CPU has been
turned OFF. (The internal ARM decides if power down is
necessary.)
LOW_PWR_RDY
63
O
Output to system to indicate iceLynx-Micro is ready to go into
a low power state. The ARM and WTCH_DG_TMRZ control
this pin.
WTCH_DG_TMRZ
88
O
Watch Dog Timer (for the ARM.) iceLynx-Micro hardware
asserts this pin whenever ARM software has not updated the
Timer2 register within the allowed time period.
RESET_ARMZ
60
I
ARM reset. This signal resets the internal ARM processor.
RESETZ
59
I/O
Device reset. This signal resets all logic. This includes the
PHY, Link core, memory, the ARM, and random logic.
VSS
1,
21,
55,
76,
102
117
131,
146,
162
176
Digital Ground.
AGND
24,
27,
35,
45,
Analog Ground.
PLL_GND
54
PLL Ground.
VDD
4,
20,
56,
75,
101
116,
130
145,
161
175
Digital Power Supply. Must be set to 3.3V nominal.
