Phytec phyCORE-MPC5200B tiny, Hardware Manual

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phyCORE-MPC5200B tiny
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PHYTEC Messtechnik GmbH 2006 L-678e_0
Internally generated voltages: 1V5, 2V5
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3 V3 PowerPC I/O, Flash memory
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2 V5 DDR SDRAM and Ethernet PHY
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1 V5 PowerPC Core
4.1 Voltage Supervision and Reset
The input voltage 3V3 as well as the on-board generated operation
voltages 2V5 and 1V5 are monitored by a voltage supervisor device at
U11. This circuitry is responsible for generation of the system reset
signal /PoReset. The voltage supervisor IC initiates a reset cycle if any
operating voltage drops below its minimum threshold value. After all
voltages reach their required value, the supervisor chip adds an
additional 200 ms delay until the /PoReset line will be inactive (high).
/PoReset connects to the processor reset input.
/PoReset is combined via the diodes D5 and D6 with /COP_TRST to a
logic OR with /CPU_TSRT (JTAG controller reset) as output. This
logic connection is used to ensure a proper reset of the CPU internal
debug interface by /PoReset or by the COP signal /COP_TRST.
The voltage supervisor's master reset input /RESIN can be connected
to an external signal or switch to release a asynchronous reset
manually.