Phytec phyCORE-MPC5200B tiny, Hardware Manual

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phyCORE-MPC5200B tiny
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PHYTEC Messtechnik GmbH 2006 L-678e_0
Pin Number Signal I/O Comments
21C RXD6_232 I RxD input on the RS-232 transceiver for the
MPC UART (PSC6)
23C TXD6_232 O TxD output on the RS-232 transceiver for the
MPC UART (PSC6)
Pin Row X1C
24C /UART6_RTS_TTL I PSC6 request to send signal
25C /UART6_CTS_TTL O PCS6 clear to send signal
26C
28C
I2C2_CLK
I2C2_IO
I/O
I/O
Second I²C Interface
Clock (SCL)
Data (SDA)
29C
30C Timer4
Timer5 I/O
I/O Timer 4 signal of the MPC5200B
Timer 5 signal of the MPC5200B
31C I2C1_CLK I/O Clock for first I2C-Interface (SCL)
33C
34C
35C
36C
38C
41C
ETH_LINK
ETH_SPEED
ETH_RX-
ETH_TX-
/ETH_PD
ET_NWAYEN
O
O
I
O
I
O
10/100MBit TP Ethernet Interface (if on-
board PHY is not populated, pins are NC)
Link/Activity LED (L=link; toggle=act)
Speed LED (H=10 Mbit/s, L=100 Mbit/s)
Differential receive input
Differential transmit output
Power down
Collision LED (H = no collision)
39C
40C
/COP_TRST
CK_STOP
I
O
JTAG Interface
JTAG reset input. Via logic OR connected to
/PORRESET resulting in /CPU_TRST signal.
Scan enable, clock stop
43C PSC2_4 I/O Freely available GPIO with wakeup function
44C Timer6 I/O Timer 6 signal of the MPC5200B
45C
46C
48C
49C
50C
USB1_OVRCRNT
USB1_SUSPEND
USB1_RXN
USB1_TXN
/USB1_OE
I
O
I
O
O
USB1 (Host)
Over current
Suspend
Receive negative
Transmit negative
Output enable
Pin Row X1D
1D, 2D +3V3 I Supply v3.3 VDC
3D, 9D, 14D,
19D, 24D, 29D,
34D, 39D, 44D,
49D GND - Ground 0 V
4D, 5D NC - Not connected
6D VCC_SRAM O VCC_SRAM supply voltage is generated by
VBAT or +3V3 using a battery backup circuit
(MAX6364). VCC_SRAM serves as supply
voltage for the Real-Time Clock.
7D RESOUT O Reset output of the voltage supervisor circuit
8D /PHYReset I A low on this pin forces only the PHY into
reset state