Phytec phyCORE-i.MX27, Hardware Manual

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phyCOREi.MX27
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©
PHYTEC Messtechnik GmbH 2011 L-710e_5
Typically the LP-DDR-SDRAM initialization is performed by a boot loader or operating system
following a power-on reset and must not be changed at a later point by any application code. When
writing custom code independent of an operating system or boot loader, SDRAM must be initialized
by accessing the appropriate SDRAM configuration registers on the i.MX27 controller.
Refer to the
i.MX27 User Manual for accessing and configuring these registers.
7.3 NOR-Flash (U17)
The phyCORE-i.MX27 can be populated with an Intel Strata Flash at U17. This NOR-Flash is
connected to /CS0 which is located at memory address 0xC000 0000. The entire Flash can be write
protected by pulling the x_/FL_WP signal, located at the phyCORE-connector X1 on pin 58B, low.
The following NOR-Flash devices can be used on the phyCORE-i.MX27:
Table 9: Compatible NOR Flash devices
M
ANUFACTURER
NOR F
LASH
P/N D
ENSITY
(MB
YTE
)
Intel PC28F640P30 8
Intel PC28F128P30 16
Intel PC28F256P30 32
7.4 NAND Flash Memory (U16)
Use of Flash as non-volatile memory on the phyCORE-i.MX27 provides an easily reprogrammable
means of code storage. The following Flash devices can be used on the phyCORE-i.MX27:
Table 10: Compatible NAND Flash devices
M
ANUFACTURER
NAND F
LASH
P/N D
ENSITY
(MB
YTE
)
ST Microelectronics NAND256R3A2BZA6 32
ST Microelectronics NAND512R3A2BZA6 64
Additionally, any parts that are footprint (VFBGA) and functionally compatible with the NAND Flash
devices listed above may also be used with the phyCORE-i.MX27.
These Flash devices are programmable with 1.8 V. No dedicated programming voltage is required.
As of the printing of this manual these NAND Flash devices generally have a life expectancy of at
least 100,000 erase/program cycles and a data retention rate of 10 years.