Phytec phyCORE-i.MX27 Hardware Manual Download Page 32

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phyCOREi.MX27

PHYTEC Messtechnik GmbH 2011 L-710e_5

Table 2:

Jumper settings

EFAULT

ETTING

LTERNATIVE

ETTING

ECTION

closed

EEPROM U12 is not write
protected

open

EEPROM U12 is write
protected

7.5.2

closed

Power up Mode select
(PUMS1) is connected to GND
(low)

open

Power up Mode select
(PUMS1) is floating

open

Power up Mode select
(PUMS1) is floating

closed

Power up Mode select
(PUMS1) is connected to
VATLAS (high)

open

Power up Mode select
(PUMS1) is floating

closed

Power up Mode select
(PUMS2) is connected to
VATLAS (high)

closed

Power up Mode select
(PUMS2) is connected to GND
(low)

open

Power up Mode select
(PUMS2) is floating

open

Power up Mode select
(PUMS3) is floating

closed

Power up Mode select
(PUMS3) is connected to
VATLAS (high)

open

Power up Mode select
(PUMS3) is floating

closed

Power up Mode select
(PUMS3) is connected to
GND (low)

Fehler!

V
e
r
w
e

s
q
u
e

l
l

k
o
n
n
t
e

c
h
t
g
e
f
u
n
d
e
n

w
e
r
d
e
n

closed

CHRGMOD1 is connected to
VATLAS (high)

open

CHRGMOD1 is floating
(high-z)

Summary of Contents for phyCORE-i.MX27

Page 1: ...A product of a PHYTEC Technology Holding company phyCORE i MX27 HARDWARE MANUAL EDITION FEBRUARY 2011 ...

Page 2: ...EC Messtechnik GmbH offers no guarantee nor accepts any liability for damages arising from the improper usage or improper installation of the hardware or software PHYTEC Messtechnik GmbH further reserves the right to alter the layout and or design of the hardware without prior notification and accepts no liability for doing so Copyright 2011 PHYTEC Messtechnik GmbH D 55129 Mainz Rights including t...

Page 3: ...33 7 1 Memory Model 33 7 2 LP DDR SDRAM U3 U4 33 7 3 NOR Flash U17 34 7 4 NAND Flash Memory U16 34 7 4 1 8 16 Bit NAND Flash Usage JN1 JN2 RN31 RN32 35 7 5 I C EEPROM U12 35 7 5 1 Setting the EEPROM Lower Address Bits J13 J15 J16 36 7 5 2 EEPROM Write Protection Control J1 36 8 Serial Interface 37 8 1 RS 232 Transceiver U18 37 8 1 1 UART1 Routing RN30 37 9 USB OTG Transceiver U20 39 10 Ethernet Co...

Page 4: ...CORE i MX27 and phyCORE i MX Carrier Board 63 14 3 1 Power Supply 63 14 3 2 CAN Interface 67 14 3 3 Push Buttons and LEDs 69 14 3 4 Compact Flash Card 71 14 3 5 Security Digital Card MultiMedia Card 73 14 3 6 Audio and Touchscreen 74 14 3 7 USB Host 76 14 3 8 LCD Connectors 78 14 3 9 Camera Interface 79 14 3 10 JTAG Interface 81 14 3 11 Complete jumper setting list for phyCORE i MX27 on the i MX C...

Page 5: ...sical dimensions 45 Figure 12 phyCORE i MX27 Carrier Board connection using the phyMAP i MX27 50 Figure 13 Modular development and Expansion Board concept with phyCORE i MX27 50 Figure 14 phyMAP i MX27 top view 51 Figure 15 phyMAP i MX27 bottom view 52 Figure 16 Jumper location on PMA 005 53 Figure 17 Physical dimensions of phyMAP i MX27 mapper 62 Figure 18 pyhCORE i MX Carrier Board and phyCORE i...

Page 6: ...011 L 710e_5 Figure 26 phyCORE i MX Carrier Board Camera Interface 79 Figure 27 phyCORE iMX Carrier Board JTAG Interface 81 Figure 28 phyCORE i MX27 component placement top view 87 Figure 29 phyCORE i MX27 component placement bottom view 88 ...

Page 7: ...2 EEPROM I C address via J13 J15 and J16 36 Table 13 EEPROM write protection states via J1 36 Table 14 RN30 UART1 signal routing 38 Table 15 Fast Ethernet controller memory map 40 Table 16 JTAG connector U15 signal assignment 43 Table 17 Jumper settings of PMA 002 53 Table 18 PMA 002 mapping list 54 Table 19 Jumper settings for i MX27 power supply via power plug 64 Table 20 Jumper settings for i M...

Page 8: ...nterface jumper settings 75 Table 29 UBS Host interface jumper settings for i MX27 module 77 Table 30 Camera interface jumper settings for i MX27 module 80 Table 31 JTAG jumper settings for phyCORE i MX27 module 81 Table 32 Jumper settings for i MX27 module on i MX Carrier Board 82 ...

Page 9: ...be operated without protection circuitry if connections to the product s pin header rows are longer than 3 m PHYTEC products fulfill the norms of the European Union s Directive for Electro Magnetic Conformity only in accordance to the descriptions and rules of usage indicated in this hardware manual particularly in respect to the pin header row connectors power connector and serial interface to a ...

Page 10: ...ing EMI and EMC guidelines using phyCORE boards even in high noise environments phyCORE boards achieve their small size through modern SMD technology and multi layer design In accordance with the complexity of the module 0402 packaged SMD components and laser drilled microvias are used on the boards providing phyCORE users with access to this cutting edge miniaturization technology for integration...

Page 11: ... data rates of up to 460kbps Full featured UART Interfaces without transceiver 32 KB I2 C EEPROM Separate I C RTC with backup function 512 Kbyte up to 2MByte SRAM with backup function Battery buffered controller based RTC with automatic battery switchover High Speed USB OTG transceiver Auto FDX MDX 100 MBit Ethernet Controller All controller required supplies generated on board by PMIC Synchronous...

Page 12: ...phyCOREi MX27 4 PHYTEC Messtechnik GmbH 2011 L 710e_5 1 2 Block Diagram Figure 1 Block Diagram of the phyCore i MX27 ...

Page 13: ...4 TP16 RN8 R10 R37 RN29 C162 C146 C118 J16 R24 J9 C27 R7 R62 C145 C173 RN19 C135 R63 C143 R78 RN25 C112 R4 D7 R90 C21 C102 D6 L5 C117 R53 U5 J15 TP1 R14 C85 TP7 C97 U3 TP12 R19 R12 R66 C99 RN17 R21 XT3 U4 D5 TP8 RN30 C151 RN22 Q7 C16 RN16 TP11 TP17 R48 C111 J1 R64 C109 C110 C140 R60 R9 J13 RN26 C20 TP2 C105 R55 C94 XT2 C150 C116 C29 C107 C104 R71 C114 U12 R8 C23 R6 Q2 RN5 RN7 RN1 RN6 U15 JN2 JN1 R...

Page 14: ... C87 C1 C133 RN9 C89 C74 J19 C2 D8 TP24 TP21 R44 C126 C68 R59 C158 L1 C156 C106 R27 J3 C25 R88 C51 TP4 C80 C125 R40 C41 J8 C75 C47 C66 Q3 R82 J6 R84 C45 R28 C79 TP26 C113 C137 C170 C69 C34 R85 C101 C86 C168 J2 U9 R38 C33 C130 R83 C63 C98 C19 C9 R34 R32 C36 R33 D4 C166 U10 C147 C165 C76 L2 R29 R16 C40 C148 C49 RN10 C30 C8 C65 Q5 R30 RN11 C64 R67 C71 C90 C169 D1 R50 C123 C78 J17 R22 C124 C82 TP22 C5...

Page 15: ...the pin connector rows progresses alphabetically from left to right refer to Figure 4 The numbered matrix can be aligned with the phyCORE i MX27 viewed from above phyCORE connector pointing down or with the socket of the corresponding phyCORE Development Board user target circuitry The upper left hand corner of the numbered matrix pin 1A is thus covered with the corner of the phyCORE i MX27 marked...

Page 16: ...1 also provides the appropriate signal level interface voltages listed in the SL Signal Level column The Freescale i MX27 is a multi voltage operated microcontroller and as such special attention should be paid to the interface voltage levels to avoid unintentional damage to the microcontroller and other on board components Please refer to the Freescale i MX27 User s Manual Data Sheet for details ...

Page 17: ... unconnected 12A GND 0 Ground 0 V 13A X_LD0 I O NVDD7_12_14 Input Output data to display 14A X_LD2 I O NVDD7_12_14 Input Output data to display 15A X_LD3 I O NVDD7_12_14 Input Output data to display 16A X_LD5 I O NVDD7_12_14 Input Output data to display 17A GND 0 Ground 0V 18A X_LD8 I O NVDD7_12_14 Input Output data to display 19A X_LD10 I O NVDD7_12_14 Input Output data to display 20A X_LD11 I O ...

Page 18: ...s D10 55A X_D11 I O NVDD1_2_3_4_5 Data_Bus D11 56A X_D13 I O NVDD1_2_3_4_5 Data_Bus D13 57A GND 0 Ground 0 V 58A X_PC_BVD1 I NVDD1_2_3_4_5 PCMCIA Battery Voltage Detect Input 1 59A X_PC_BVD2 I NVDD1_2_3_4_5 PCMCIA Battery Voltage Detect Input 2 60A X_ PC_CD1 I NVDD1_2_3_4_5 PCMCIA Card Detect Input 1 61A X_PC_PWRON I NVDD1_2_3_4_5 PCMCIA Power is ON Signal 62A GND 0 Ground 0 V 63A X_ PC_RW O NVDD1...

Page 19: ...er Clock 85A X_CSI_VSYNC I NVDD11 Camera Sensor vertical sync 86A X_CSI_PIXCLK I NVDD11 Camera Sensor data latch clock 87A GND 0 Ground 0 V 88A X_KP_COL0 I O NVDD6_8_9_10 Keypad Port Column 0 89A X_KP_COL1 I O NVDD6_8_9_10 Keypad Port Column 1 90A X_KP_COL2 I O NVDD6_8_9_10 Keypad Port Column 2 91A X_KP_ROW0 I O NVDD6_8_9_10 Keypad Port Row 0 92A GND 0 Ground 0 V 93A X_KP_ROW3 I O NVDD6_8_9_10 Key...

Page 20: ...y 16B X_LD6 I O NVDD7_12_14 Input Output data to display 17B X_LD7 I O NVDD7_12_14 Input Output data to display 18B X_LD9 I O NVDD7_12_14 Input Output data to display 19B GND 0 Ground 0 V 20B X_LD12 I O NVDD7_12_14 Input Output data to display 21B X_LD14 I O NVDD7_12_14 Input Output data to display 22B X_LD15 I O NVDD7_12_14 Input Output data to display 23B X_LD16 I O NVDD7_12_14 Input Output data...

Page 21: ...6B X_D14 I O NVDD1_2_3_4_5 Data_Bus D14 57B X_D15 I O NVDD1_2_3_4_5 Data_Bus D15 58B X_ FL_WP I Flash Protection Signal 59B GND 0 Ground 0 V 60B X_ PC_CD2 I NVDD1_2_3_4_5 PCMCIA Card Detect Input 2 61B X_PC_POE O NVDD1_2_3_4_5 PCMCIA buffers output enable 62B X_PC_READY I NVDD1_2_3_4_5 PCMCIA Ready 63B X_PC_RST O NVDD1_2_3_4_5 PCMCIA Card Reset 64B GND 0 Ground 0 V 65B X_ PC_WAIT I NVDD1_2_3_4_5 P...

Page 22: ...t Ethernet Transmit Data 0 87B X_FEC_TXD1 O NVDD6_8_9_10 Fast Ethernet Transmit Data 1 88B NVDD6_8_9_10 O NVDD6_8_9_10 Keypad reference voltage 2 775 V 89B GND 0 Ground 0 V 90B X_KP_COL3 I O NVDD6_8_9_10 Keypad Port Column 3 91B X_KP_ROW1 I O NVDD6_8_9_10 Keypad Port Row 1 92B X_KP_ROW2 I O NVDD6_8_9_10 Keypad Port Row 2 93B X_KP_ROW4 I O NVDD6_8_9_10 Keypad Port Row 4 94B GND 0 Ground 0V 95B X_KP...

Page 23: ...t 1 15C X_BATTFET O VATLAS Driver output for battery path FET 16C X_CHRGISNSP I VATLAS Charge current sensing point 1 17C GND 0 Ground 0 V 18C X_BKUP_SUPPLY I MV 1 Coincell supply input 2 Coincell charger output 19C X_CHRGLED O EHV Trickle LED driver output 20C X_CHRGMOD0 I VATLAS Selection of the mode of charging 21C X_CHRGMOD1 I VATLAS Selection of the mode of charging 22C GND 0 Ground 0 V 23C X...

Page 24: ...nput Channel 7 47C GND 0 Ground 0 V 48C X_ADOUT O LV ADC trigger output 49C X_ADTRIG I LV ADC trigger input 50C X_ LOWBAT O LV Low battery detection signal 51C X_USEROFF I LV Signal from processor to confirm user off mode after a power fail 52C GND 0 Ground 0 V 53C X_VBUS I O 5V SW3 USB VBUS Voltage 54C X_UDM I O 3 3V USB transceiver cable interface D 55C X_UDP I O 3 3V USB transceiver cable inter...

Page 25: ...ot connected Pin left unconnected 81C not connected Pin left unconnected 82C GND 0 Ground 0 V 83C X_I2C2_SCL I O NVDD7_12_14 I C 2 Serial Clock 84C X_I2C2_SDA I O NVDD7_12_14 I C 2 Serial Data 85C X_I2C_DATA I O NVDD7_12_14 I C 1 Serial Data 86C X_CSPI1_SCLK I O NVDD6_8_9_10 SPI 1 clock 87C GND 0 Ground 0 V 88C X_CSPI1_SS1 I O NVDD6_8_9_10 SPI 1 Chip select 1 89C X_CSPI3_MOSI I O NVDD6_8_9_10 SPI ...

Page 26: ...ut 13D X_CHARGER_INPUT_ 3 20V I EHV Charger Input 14D GND 0 Ground 0 V 15D X_CHRGISNSN I VATLAS Charge current sensing point 2 16D X_BFET O EHV 1 Driver output for dual path regulated BP FET 2 Driver output for separate USB charger path FET 17D X_CHRGCTL O EHV Driver output for charger path FET s 18D X_PWRRDY O LV Power ready signal after DVS and power gate transition 19D GND 0 Ground 0 V 20D X_GP...

Page 27: ...Analog Input Channel 8 46D X_ADIN9 I LV Analog Input Channel 9 47D X_ADIN10 I LV Analog Input Channel 10 48D X_ADIN11 I LV Analog Input Channel 11 49D GND 0 Ground 0 V 50D X_USBH1_RXDM I NVDD7_12_14 USB Host1 Receive Data Minus signal 51D X_USBH1_RXDP I NVDD7_12_14 USB Host1 Receive Data Plus signal 52D X_USBH1_TXDM O NVDD7_12_14 USB Host1 Transmit Data Minus signal 53D X_USBH1_TXDP O NVDD7_12_14 ...

Page 28: ...Primary Interrupt output of PMIC U14 82D X_ IRQRTC O NVDD6_8_9_10 Interrupt Output from RTC U11 RTC 8564JE 83D NVDD6_8_9_10 O NVDD6_8_9_10 I2C reference voltage 2 775 V 84D GND 0 Ground 0 V 85D X_I2C_CLK I O NVDD6_8_9_10 I C 1 Serial Clock 86D X_CSPI1_MOSI I O NVDD6_8_9_10 SPI 1 Master data out slave data in 87D X_CSPI1_MISO I O NVDD6_8_9_10 SPI 1 Master data in slave data out 88D X_CSPI3_SCLK NVD...

Page 29: ...of the solder jumpers on the board 8 solder jumpers are located on the top side of the module opposite side of connectors and 16 solder jumpers are located on the bottom side of the module connector side Table 2 below provides a functional summary of the solder jumpers their default positions and possible alternative positions and functions A detailed description of each solder jumper can be found...

Page 30: ...phyCOREi MX27 22 PHYTEC Messtechnik GmbH 2011 L 710e_5 J21 J16 J9 J15 J1 J13 JN2 JN1 Figure 6 Jumper locations top view ...

Page 31: ...Jumpers PHYTEC Messtechnik GmbH 2011 L 710e_5 23 J12 J17 J14 J11 J5 J22 J18 J4 J7 J19 J3 J8 J6 J2 J10 J20 Figure 7 Jumper locations bottom view The jumpers J solder jumper have the following functions ...

Page 32: ...ted to VATLAS high J4 open Power up Mode select PUMS1 is floating closed Power up Mode select PUMS2 is connected to VATLAS high J5 closed Power up Mode select PUMS2 is connected to GND low open Power up Mode select PUMS2 is floating J6 open Power up Mode select PUMS3 is floating closed Power up Mode select PUMS3 is connected to VATLAS high J7 open Power up Mode select PUMS3 is floating closed Powe...

Page 33: ...5 J17 2 3 RXOUTR is connected to X_RXOUTR_LSPM X1 Pin 24C 1 2 LSPM is connected to X_RXOUTR_LSPM X1 Pin 24C J18 2 3 RXOUTL is connected to X_RXOUTL_LSPP X1 Pin 23C 1 2 LSPP is connected to X_RXOUTL_LSPP X1 Pin 23C J19 2 3 DS75 A2 is connected to GND low 1 2 DS75 A2 is connected to NVDD7_12_14 high J20 1 3 SRAM_BHE is connected to X_ PC_IORD EB1 2 4 X_ PC_REG EB0 is connected to SRAM_BLE 1 2 SRAM_B...

Page 34: ...phyCOREi MX27 26 PHYTEC Messtechnik GmbH 2011 L 710e_5 ...

Page 35: ...VCC_3V3 from VIN with a 3 3 V voltage regulator on the Carrier Board VIN is sourced from either the wall socket input or a battery The Carrier Board also controls charging the battery when the wall socket is used You should refer to this example circuitry when designing your own Carrier Board If your system does not require a battery then you can connect VIN and VCC_3V3 together and supply both in...

Page 36: ...ins which are neighboring signals being used in the application circuitry The i MX27 CPU is supplied by a lot of different power domains Some of them are connected together The startup voltage levels are selected by the Power up Mode selection inputs PUMS1 3 of the PMIC device MC13783 With the default settings of the input pins PUMS1 3 the voltages are the following Table 4 i MX27 default power in...

Page 37: ...UP2 of MC13783 To set the output voltage and the different modes of VBKUP2 U14 MC13783 must be programmed over SPI Table 5 VBKUP2 Voltage Settings 00 output 1 0 V 01 output 1 2 V 10 output 1 5 V VBKUP2 1 0 11 output 1 8 V There are three bits which must be set to low high for the different modes of VBKUP2 VBKUP2EN Enables VBKUP2 in startup modes on and user off wait modes VBKUP2AUTOMH Enables VBKU...

Page 38: ...phyCOREi MX27 30 PHYTEC Messtechnik GmbH 2011 L 710e_5 ...

Page 39: ...ettings are necessary 6 1 1 Power Up Mode Select PUMS The Power Management IC M13783 has three Power Up Mode Selecets PUMS1 and PUMS2 determine the initial setup for the voltage level of the switchers and regulators and if they get enabled or not With PUMS3 three different power up sequences are selectable The three states of the PUMS settings are Pull up connected to VATLAS Pull down connected to...

Page 40: ...able 7 Boot Modes of i MX27 module Boot Mode Selection Boot Mode Device 0000 Bootstrap from UART USB 0001 Reserved 0010 8 bit NAND Flash 2 Kbyte per page 0011 16 bit Nand Flash 2 Kbyte per page 0100 16 bit Nand Flash 512 bytes per page 0101 16 bit CS0 NOR Flash 0110 32 bit CS0 0111 8 bit Nand Flash 512 bytes per page 1xxx Reserved The phyCORE i MX27 module comes with a standard boot configuration ...

Page 41: ... 8 i MX27 memory map ADDRESS CHIP SELECT FUNCTION 0xA000 0000 0xAFFF FFFF CSD0 CS2 LP DDR SDRAM Bank 0 U3 U4 0xB000 0000 0xBFFF FFFF CSD1 CS3 not used on phyCORE i MX27 0xC000 0000 0xC7FF FFFF CS0 NOR Flash U17 0xC800 0000 0xCFFF FFFF CS1 SRAM U19 0xD400 0000 0xD5FF FFFF CS4 not used on phyCORE i MX27 0xD600 00000 0xD7FF FFFF CS5 not used on phyCORE i MX27 SJA1000 on Carrier Board 7 2 LP DDR SDRAM...

Page 42: ...low The following NOR Flash devices can be used on the phyCORE i MX27 Table 9 Compatible NOR Flash devices MANUFACTURER NOR FLASH P N DENSITY MBYTE Intel PC28F640P30 8 Intel PC28F128P30 16 Intel PC28F256P30 32 7 4 NAND Flash Memory U16 Use of Flash as non volatile memory on the phyCORE i MX27 provides an easily reprogrammable means of code storage The following Flash devices can be used on the phy...

Page 43: ...general purpose data This device is accessed through I C port 2 on the i MX27 The serial clock signal and serial data signal for I C port 2 are made available at the phyCORE connector as x_I2C2_SDA on X1 pin 84C and x_I2C2_SCL on X1 pin 83C Three solder jumpers are provided to set the lower address bits J13 J15 and J16 Refer to section 7 5 1 for details on setting these jumpers Write protection to...

Page 44: ...lting seven bit I C device address for the eight possible jumper configurations Table 12 U12 EEPROM I C address via J13 J15 and J161 U12 I C DEVICE ADDRESS J15 J13 J16 1010 010 2 3 2 3 2 3 1010 011 2 3 2 3 1 2 1010 000 2 3 1 2 2 3 1010 001 2 3 1 2 1 2 1010 110 1 2 2 3 2 3 1010 111 1 2 2 3 1 2 1010 100 1 2 1 2 2 3 1010 101 1 2 1 2 1 2 7 5 2 EEPROM Write Protection Control J1 Jumper J1 controls writ...

Page 45: ...e supplied by the user if additional UART s require RS 232 levels The maximum baud rate of UART1 is limited to 460 800 bps when used with the on board MAX3380 RS 232 transceiver 8 1 1 UART1 Routing RN30 RN30 is used to route the signals of UART1 serial interface through the RS 232 transceiver or around the RS 232 transceiver when populated When RN30 is not populated UART1_RXD UART1_TXD UART1_RTS a...

Page 46: ...2 X_UART1_TXD_RS232 X_UART1_ RTS_RS232 X_ UART1_CTS_RS232 as RS 232 level signals at X1 pin 22D X1 pin 23D X1 pin 25D and X1 pin 26D not populated X_UART1_RXD_RS232 X_UART1_TXD_RS232 X_UART1_ RTS_RS232 X_ UART1_CTS_RS232 as TTL level signals at X1 pin 22D X1 pin 23D X1 pin 25D and X1 pin 26D populated 1 Defaults are in bold blue text ...

Page 47: ...low speed data rates The ISP1504 functions as the transceiver between the i MX27 Host Controller Device Controller and On The Go Controller An external USB Standard A for USB host USB Standard B for USB device or USB mini AB for USB OTG connector is all that is needed to interface the phyCORE i MX27 USB OTG functionality The applicable interface signals D D VBUS ID can be found in the phyCORE conn...

Page 48: ...X pins of the connected device and automatically configures the PHY TX and RX pins accordingly The Ethernet Phy also features LinkMD cable diagnostics which allows detection of common cabling plant problems such as open and short circuits The physical memory area for the Fast Ethernet controller is defined in Table 15 Table 15 Fast Ethernet controller memory map ADDRESS FUNCTION 0x1002_B 0x000 1FF...

Page 49: ...into the external flash internal controller RAM or for debugging programs currently executing The JTAG interface extends out to a 2 0 mm pitch pin header at U15 on the edge of the module PCB Figure 9 and Figure 10 show the position of the debug interface JTAG connector U15 on the phyCORE module U15 2 10 4 6 8 12 14 16 18 20 Figure 9 JTAG interface at U15 top view ...

Page 50: ...e The JTAG connector U15 only populates phyCORE i MX27 modules with order code PCM 038 D JTAG connector U15 is not populated on phyCORE modules with order code PCM 038 However all JTAG signals are also accessible at the phyCORE connector X1 Molex connectors We recommend integration of a standard 2 54 mm pitch pin header connector in the user target circuitry to allow easy program updates via the J...

Page 51: ...mulator adapter extends the signals of the module s JTAG connector to a standard ARM connector with 2 54 mm pin pitch The JA 002 therefor functions as an adapter for connecting the module s non ARM compatible JTAG connector U15 to standard Emulator connectors PIN ROW SIGNAL A B SIGNAL VCC NVDD6_8_9_10 2 1 VTref NVDD6_8_9_10 via 100 Ohm GND 4 3 X_ TRST GND 6 5 X_TDI GND 8 7 X_TMS GND 10 9 X_TCK GND...

Page 52: ...phyCOREi MX27 44 PHYTEC Messtechnik GmbH 2011 L 710e_5 ...

Page 53: ...ule s profile is approximately 8 5 mm thick with a maximum component height of 4 0 mm on the bottom connector side of the PCB and approximately 3 1 mm on the top microcontroller side The board itself is approximately 1 4 mm thick 0 635mm 3 6mm 3 7mm 2 35mm 84mm 77 47mm 77 15mm 75 1mm 10 58mm 8 93mm 6 88mm 3 28mm 60mm 55 35mm 53 85mm 6 25mm 4 75mm Figure 11 Physical dimensions ...

Page 54: ... temperature 0 C to 70 C standard 20 C to 85 C optional Humidity 95 r F not condensed Operating voltage VIN 3 1 V to 4 6 V Power consumption VCC_3V3 43 mA typical VIN 100 mA typical Conditions VCC_3V3 3 3 V VIN 4 25 V 256 kByte SRAM 32 MByte Flash 128 MB LP DDR RAM 64 MB NAND Flash Ethernet 400 MHz CPU frequency at 20 C These specifications describe the standard configuration of the phyCORE i MX27...

Page 55: ...dule Should this nonetheless be necessary please ensure that the board as well as surrounding components and sockets remain undamaged while de soldering Overheating the board can cause the solder pads to loosen rendering the module inoperable Carefully heat neighboring connections in pairs After a few alternations components can be removed with the solder iron tip Alternatively a hot air gun can b...

Page 56: ...phyCOREi MX27 48 PHYTEC Messtechnik GmbH 2011 L 710e_5 ...

Page 57: ...ow the phyCORE i MX27 module works with the phyCORE i MX Carrier Board how both boards are connected together over the phyMAPPER and you will also find all settings that have to be done for a speedy and secure start up of your i MX27 module In this chapter you will only find specialized information of how the phyCORE i MX27 module works with the phyCORE i MX Carrier Board For further information a...

Page 58: ...a phyMAPPER that is mapping the signals of the i MX module to the i MX Carrier Board An example of the concept is shown in Figure 12 below For further information about the concept of the i MX Carrier Board refer to the i MX Carrier Board Hardware Manual Figure 12 phyCORE i MX27 Carrier Board connection using the phyMAP i MX27 Figure 13 below illustrates the modular development platform concept Fi...

Page 59: ...along with signal differences between the phyCORE i MX module connectors and i MX Carrier Board connector do not allow for direct connection of the phyCORE i MX modules into a single standardized Carrier Board To allow for the use of a single Carrier Board despite the signal differences the phyMAP i MX27 board serves as the gateway to properly map signals from the i MX Carrier Board Molex connecto...

Page 60: ...phyCOREi MX27 52 PHYTEC Messtechnik GmbH 2011 L 710e_5 X2 X2 X2 Figure 15 phyMAP i MX27 bottom view ...

Page 61: ... backup power supply device is the goldcap C161 of the Carrier Board If J1 is set to 2 3 the backup power is provided by a Li Cell at connector X20 of the Carrier Board J2 Whether the Phytec provided Sharp Display or the Hitachi Display is used with the i MX27 Development Kit this jumper has to be set to the right position In position 1 2 the X_OE_ACD signal for the Hitachi Display is connected to...

Page 62: ...D X_ BATTDET 43C 25E x_EXP038 X_ CSD1 25B 2F x_EXP002 X_ CSPI1_RDY 90C 41F x_EXP065 X_ CS0 24A 1E x_EXP000 X_ CS1 25A 1F x_EXP001 X_ CS4 26A 58A 3E x_ CS_CAN x_EXP003 X_ CS5 26B 3F x_EXP004 X_ ECB 30B 4E x_EXP005 X_ FL_WP 58B 49E x_EXP077 X_ IRQRTC 82D 45E x_EXP070 X_ LBA 30A 54A x_LBA X_ LOWBAT 50C 31E x_EXP048 X_ ON1 30C 55D x_ ON1 X_ ON2 31C 56C x_ ON2 X_ ON3 37D 56D x_ ON3 X_ PC_CD1 60A 66A x_...

Page 63: ...X_A6 35B 31A x_A6 X_A7 36A 31B x_A7 X_A8 36B 32B x_A8 X_A9 37B 33A x_A9 X_A10 38A 33B x_A10 X_A11 38B 34A x_A11 X_A12 39A 35A x_A12 X_A13 40A 35B x_A13 X_A14 40B 36A x_A14 X_A15 41A 36B x_A15 X_A16 41B 37B x_A16 X_A17 42B 38A x_A17 X_A18 43A 38B x_A18 X_A19 43B 39A x_A19 X_A20 44A 40A x_A20 X_A21 45A 40B x_A21 X_A22 45B 41A x_A22 X_A23 46A 41B x_A23 X_A24 46B 42B x_A24 X_A25 47B 43A x_A25 X_BATTFE...

Page 64: ...A 75A x_CSI_D2 X_CSI_D1 78B 75B x_CSI_D3 X_CSI_D2 79A 76A x_CSI_D4 X_CSI_D3 80A 76B x_CSI_D5 X_CSI_D4 80B 77B x_CSI_D6 X_CSI_D5 81A 78A x_CSI_D7 X_CSI_D6 81B 78B x_CSI_D8 X_CSI_D7 82B 79A x_CSI_D9 X_CSI_HSYNC 85B 73B x_CSI_HSYNC X_CSI_MCLK 84A 69A x_CSI_MCLK X_CSI_PIXCLK 86A 71B x_CSI_PCLK X_CSI_VSYNC 85A 72B x_CSI_VSYNC X_CSPI1_MISO 87D 96B x_MISO X_CSPI1_MOSI 86D 95B x_MOSI X_CSPI1_SCLK 86C 97B ...

Page 65: ...019 X_FEC_RXD1 70B 8F x_EXP012 X_FEC_RXD2 71A 9E x_EXP013 X_FEC_RXD3 71B 10E x_EXP014 X_FEC_RX_CLK 76A 14E x_EXP021 X_FEC_RX_DV 75B 13F x_EXP020 X_FEC_RX_ER 70A 8E x_EXP011 X_FEC_TXD0 86B 16F x_EXP025 X_FEC_TXD1 87B 17F x_EXP026 X_FEC_TXD2 68B 6F x_EXP009 X_FEC_TXD3 69A 7F x_EXP010 X_FEC_TX_CLK 74A 12F x_EXP018 X_FEC_TX_EN 83B 16E x_EXP024 X_FEC_TX_ER 77B 15F x_EXP023 X_GPO1 20D 21F x_EXP033 X_GPO...

Page 66: ...X_KP_ROW4 93B 47D x_KEY_ROW4 X_KP_ROW5 94A 48C x_KEY_ROW5 X_LD0 13A 13A x_LC_D0 X_LD1 13B 13B x_LC_D1 X_LD2 14A 14A x_LC_D2 X_LD3 15A 15A x_LC_D3 X_LD4 15B 15B x_LC_D4 X_LD5 16A 16A x_LC_D5 X_LD6 16B 16B x_LC_D6 X_LD7 17B 17B x_LC_D7 X_LD8 18A 18A x_LC_D8 X_LD9 18B 18B x_LC_D9 X_LD10 19A 19A x_LC_D10 X_LD11 20A 20A x_LC_D11 X_LD12 20B 20B x_LC_D12 X_LD13 21A 21A x_LC_D13 X_LD14 21B 21B x_LC_D14 X_...

Page 67: ...E21 3B 43E x_EXP067 X_PE22 2B 41E x_EXP064 X_PE23 1B 40F x_EXP063 X_POWER_BATT 13C 15D x_Power_BATT X_PRIINT 81D 69C x_EXP082 X_PS 10A 10A x_LC_DRDY0 X_PWMO 100D 45F x_EXP071 X_PWRRDY 18D 6E x_EXP008 X_REV 8A 8A x_LC_D3_REV X_RXINL 25C 25C x_RXINL X_RXINR 26C 26C x_RXINR X_RXOUTL_LSPP 23C 23C x_RXOUTL X_RXOUTR_LSPM 24C 24C x_RXOUTR X_SD2_CLK 70D 91A x_SD1_CLK X_SD2_CMD 68D 90B x_SD1_CMD X_SD2_D0 6...

Page 68: ... X_UDM 54C 34C x_UDM X_UDP 55C 35C x_UDP X_UID 56C 36C x_UID X_USBH1_FS 76D 36E x_EXP056 X_USBH1_RCV 55D 34E x_EXP053 X_USBH1_RXDM 50D 31F x_EXP049 X_USBH1_RXDP 51D 32F x_EXP050 X_USBH1_SUSP 58D 35E x_EXP054 X_USBH1_TXDM 52D 33E x_EXP051 X_USBH1_TXDP 53D 33F x_EXP052 X_USBH2_CLK 60C 83A x_USBHOST2_CLK X_USBH2_DATA0 62D 85A x_USBHOST2_DA0 X_USBH2_DATA1 63D 85B x_USBHOST2_DA1 X_USBH2_DATA2 63C 86A x...

Page 69: ... X_USEROFF 51C 21E x_EXP032 X_VBUS 53C 33C x_VBUS X_VSYNC 5A 5B x_LC_FPFRAME Note Signals in bold text are connected to jumpers The mapping of this signals could differ from the mapping list Please check the positions of the affected jumpers to find out how the signals are mapped ...

Page 70: ...H 2011 L 710e_5 14 2 3 phyMAP i MX27 Mapper Physical Dimensions 80 5mm 11 56mm 7 84mm 70mm 102mm 77 37mm 50 6mm 1 64mm 2mm 3 6mm 1 65mm 2mm 47 6mm 66 17mm 1 65mm 2mm 3 65mm 70 17mm 19 4mm Figure 17 Physical dimensions of phyMAP i MX27 mapper ...

Page 71: ... B oot M ode C LK S el P ow er O n S uspend R eset S t andby A t t ent ion see m anual R S 232 aut oshut dow n P 1 V C C C F 1 M A I N LI C ell B A C K U P LI C ell 5VD C3A D I S P LA Y M A TR I XK E Y B O A R D JTA G C A N U S B O TG S E R I A L 1 2 1 W I R E C O M P A C T FLA S H M M C S D C A M E R A LC D S W R S 232 disable U S B Line O U T Line I N M I C P H Y TE C P C M 970 S N D M C C H A R...

Page 72: ...o power switching direct supply of VCC_3V3 Separate supply path JP33 1 2 3 4 open open No power switching direct supply from VCC_3V3 Separate supply path JP34 1 2 3 4 open open No power switching direct supply from VCC_3V3 Separate supply path JP35 open closed VCC_5V Power Supply is enabled VCC_5V Power Supply is disabled JP36 open closed VCC_3V3 Power Supply is disabled VCC_3V3 Power Supply is en...

Page 73: ... 3 4 open open No power switching direct supply from VCC_3V3 Separate supply path JP34 1 2 3 4 open open No power switching direct supply from VCC_3V3 Separate supply path JP35 open closed VCC_5V Power Supply is enabled VCC_5V Power Supply is disabled JP36 open closed VCC_3V3 Power Supply is disabled VCC_3V3 Power Supply is enabled JP38 1 2 3 4 open open Power switching supply from 5 V adapter or ...

Page 74: ...upply path JP33 1 2 3 4 open open No power switching direct supply from VCC_3V3 Separate supply path JP34 1 2 3 4 open open No power switching direct supply from VCC_3V3 Separate supply path JP35 open closed VCC_5V Power Supply is enabled VCC_5V Power Supply is disabled JP36 open closed VCC_3V3 Power Supply is disabled VCC_3V3 Power Supply is enabled JP38 1 2 3 4 open open Power switching supply f...

Page 75: ...U S B O TG S E R I A L 1 2 1 W I R E C O M P A C T FLA S H M M C S D C A M E R A LC D S W R S 232 disable U S B Line O U T Line I N M I C P H Y TE C P C M 970 S N D M C C H A R G E R G P I O V I N 3V 3 5V C har ging P L 1280 4 JP7 JP8 JP10 P2 JP9 JP11 Figure 19 phyCORE i MX Carrier Board CAN Interface The phyCORE i MX27 does not provide a CAN controller For CAN support there is a CAN controller av...

Page 76: ... by VCC_CAN Digital Isolator supply is VCC_5V JP9 1 2 2 3 CANV is connected to GND of i MX Carrier Board CANV is not connected to GND of i MX Carrier Board JP10 1 2 2 3 CANRxd signal is routed to the CAN transceiver x_CAN_RxD signal is routed to the CAN transceiver JP11 1 2 2 3 CANV is connected to VCC_5V of i MX Carrier Board CANV is connected to CAN_OUT external supply 9 Default settings for the...

Page 77: ...I R E C O M P A C T FLA S H M M C S D C A M E R A LC D S W R S 232 disable U S B Line O U T Line I N M I C P H Y TE C P C M 970 S N D M C C H A R G E R G P I O V I N 3V 3 5V C har ging P L 1280 4 S5 D21 D22 D23 D40 D41 S4 S3 S2 S1 D50 D24 D19 D20 D42 Figure 20 phyCORE i MX Carrier Board Buttons and LEDs The GPIO signal to drive the User LED D40 high or low is the X_PE18 signal of the i MX27 module...

Page 78: ...s possible to select the status of BOOT0 BOOT1 and BOOT2 For detailed information see Table 23 Table 24 and Table 25 below Note A standard Boot Configuration is already set on the i MX27 module Here you can change the Boot Mode to an alternatively mode For standard Boot Configuration all dip switches have to be in OFF position Table 23 x_BOOT_MODE0 selection STATE OF SW NUMBER 3 STATE OF SW NUMBER...

Page 79: ...XK E Y B O A R D JTA G C A N U S B O TG S E R I A L 1 2 1 W I R E C O M P A C T FLA S H M M C S D C A M E R A LC D S W R S 232 disable U S B Line O U T Line I N M I C P H Y TE C P C M 970 S N D M C C H A R G E R G P I O V I N 3V 3 5V C har ging P L 1280 4 JP604 JP602 JP17 JP4 JP5 X10 Figure 21 Compact Flash Card Interface The GPIO signal of the i MX27 module connected to signal x_EXP007 of the i M...

Page 80: ...om controller to CF JP5 closed open Compact Flash is Master Compact Flash is Slave JP17 open closed Output 2 of U15 is active Output 2 of U15 is disabled JP602 closed open PC_RW non inverted PC_RW inverted JP604 closed open Power supply of CF is forced active Power supply of CF can be managed by GPIO signal x_EXP007 1 Default settings for the phyCORE i MX27 CF interface on the i MX Carrier Board a...

Page 81: ...o GPIO MMC_WP signal of SD MMC Interface is not connected to GPIO JP18 2 3 1 2 Level shifter U25 is enabled Level shifter U25 is disabled 1 Default settings for the phyCORE i MX27 SD MMC interface are in bold blue CAN PLD VCC LCD C D A B SJC Mode 1 1 1 1 1 CAN pwr CAN by Boot Mode CLK Sel Power On Suspend Reset Standby Attention see manual RS232 autoshutdown P1 VCC CF 1 MAIN LI Cell BACKUP LI Cell...

Page 82: ...S 232 disable U S B Line O U T Line I N M I C P H Y TE C P C M 970 S N D M C C H A R G E R G P I O V I N 3V 3 5V C har ging P L 1280 4 X23 X13 X12 X11 JP24 JP23 JP20 JP19 JP21 JP22 JP48 JP49 JP28 JP25 JP27 JP26 JP47 Figure 23 phyCORE i MX Carrier Board Audio Touch Interface With the phyCORE i MX27 module the MC13783 Power Management IC is used that has audio and touch functions integrated So the i...

Page 83: ...2 x_TSY1 is connected to X23 TP_Y is connected to X23 JP26 2 3 1 2 x_TSX2 is connected to X23 TP_X is connected to X23 JP27 2 3 1 2 x_TSY2 is connected to X23 TP_Y is connected to X23 JP28 2 3 1 2 X_TSX1 is connected to X23 TP_X is connected to X23 JP47 open closed Reset is held high no asserting by GPIO of i MX module Reset can be asserted by GPIO of i MX module JP48 open closed No access to IRQ ...

Page 84: ... L 1 2 1 W I R E C O M P A C T FLA S H M M C S D C A M E R A LC D S W R S 232 disable U S B Line O U T Line I N M I C P H Y TE C P C M 970 S N D M C C H A R G E R G P I O V I N 3V 3 5V C har ging P L 1280 4 X17 JP45 JP46 JP44 JP6 J13 JP42 JP43 Figure 24 phyCORE iMX Carrier Board USB Host Interface The i MX27 controller supports control of input USB devices such as keyboard mouse or USB key To real...

Page 85: ... Host is managed on the i MX module JP43 1 2 2 3 USB Host is managed on the i MX baseboard USB Host is managed on the i MX module JP44 open closed USB Host is managed on the i MX module USB Host is managed on the i MX baseboard JP45 1 2 2 3 USB Host is managed on the i MX baseboard USB Host is managed on the i MX module JP46 1 2 2 3 USB Host is managed on the i MX baseboard USB Host is managed on ...

Page 86: ...I R E C O M P A C T FLA S H M M C S D C A M E R A LC D S W R S 232 disable U S B Line O U T Line I N M I C P H Y TE C P C M 970 S N D M C C H A R G E R G P I O V I N 3V 3 5V C har ging P L 1280 4 X22 X23 SW1 Figure 25 phyCORE i MX Carrier Board LCD Interfaces The phyCORE i MX27 module comes with a 18 bit LCD interface This 18 bit LCD interface is fully connected to the molex connectors X1 of the i...

Page 87: ...24 of the i MX27 module CAN PLD VCC LCD C D A B SJC Mode 1 1 1 1 1 CAN pwr CAN by Boot Mode CLK Sel Power On Suspend Reset Standby Attention see manual RS232 autoshutdown P1 VCC CF 1 MAIN LI Cell BACKUP LI Cell 5V DC 3A DISPLAY MATRIX KEYBOARD JTAG CAN USB OTG SERIAL 1 2 1 WIRE COMPACT FLASH MMC SD CAMERA LCD SW RS232 disable USB Line OUT Line IN MIC PHYTEC PCM 970 S N DMC CHARGER GPIO VIN 3V3 5V ...

Page 88: ...ce camera sensor specific I C address For more information refer to the manual of the used camera sensor JP15 1 2 2 3 Use of Camera Connector X7 with VCC_CAM supply 3 3V Use of Camera Connector X8 with external VCC_CAM_EXT supply 14 3 9 1 PHYTEC Camera Connector Note i MX27 only has an 8 bit camera interface so you need to have a Camera Sensor with internal multiplexer When ordering a Phytec Camer...

Page 89: ...ule1 JUMPER SETTING DESCRIPTION JP12 open closed JTAG Controller is in ARM926 Platform mode JTAG Controller is in i MX27 JTAG Controller mode 1 Default Settings for the phyCORE i MX27 JTAG Interface are in bold blue CAN PLD VCC LCD C D A B SJC Mode 1 1 1 1 1 CAN pwr CAN by Boot Mode CLK Sel Power On Suspend Reset Standby Attention see manual RS232 autoshutdown P1 VCC CF 1 MAIN LI Cell BACKUP LI Ce...

Page 90: ...t is not controllable USBH2 transceiver Reset is controllable via GPIO JP7 1 2 2 3 CAN is managed on the Carrier Board CAN is managed on the module JP8 1 2 2 3 CAN signals is are on the level VCC_CAN from mapper CAN signals is are on the level VCC_5V JP9 1 2 2 3 CAN is supplied via on Board 5 V Power Supply CAN is supplied via an external Power Supply JP10 1 2 2 3 CAN is managed on the Carrier Boa...

Page 91: ...board Touch screen is managed on the module JP27 1 2 2 3 Touch screen is managed on the baseboard Touch screen is managed on the module JP28 1 2 2 3 Touch screen is managed on the baseboard Touch screen is managed on the module JP29 1 2 2 3 Backup voltage is supplied by ext LICELL Backup voltage is supplied by onboard Goldcap JP30 1 2 3 4 5 6 VCC_BOOT is deep sleep test voltage VCC_CLK is deep sle...

Page 92: ...the module USB Host is managed on the baseboard JP45 1 2 2 3 USB Host is managed on the baseboard USB Host is managed on the module JP46 1 2 2 3 USB Host is managed on the baseboard USB Host is managed on the module JP47 open closed Reset of audio touch device is not controllable Reset of audio touch device is controllable via GPIO JP48 open closed IRQ of audio touch device is not controllable IRQ...

Page 93: ...l 30 June 2009 Manual L 710e_4 PCM 038 PCB 1281 2 PCM 970 PCB 1280 4 Preliminary documentation Describes the phyCORE i MX27 with phyMAP i MX27 and i MX Carrier Board 16 February 2011 Manual L 710e_5 PCM 038 PCB 1281 4 PCM 970 PCB 1280 4 Documentation Describes the phyCORE i MX27 with phyMAP i MX27 and i MX Carrier Board ...

Page 94: ...phyCOREi MX27 86 PHYTEC Messtechnik GmbH 2011 L 710e_5 ...

Page 95: ...4 R72 RN24 TP16 RN8 R10 R37 RN29 C162 C146 C118 J16 R24 J9 C27 R7 R62 C145 C173 RN19 C135 R63 C143 R78 RN25 C112 R4 D7 R90 C21 C102 D6 L5 C117 R53 U5 J15 TP1 R14 C85 TP7 C97 U3 TP12 R19 R12 R66 C99 RN17 R21 XT3 U4 D5 TP8 RN30 C151 RN22 Q7 C16 RN16 TP11 TP17 R48 C111 J1 R64 C109 C110 C140 R60 R9 J13 RN26 C20 TP2 C105 R55 C94 XT2 C150 C116 C29 C107 C104 R71 C114 U12 R8 C23 R6 Q2 RN5 RN7 RN1 RN6 U15 ...

Page 96: ...8 C87 C1 C133 RN9 C89 C74 J19 C2 D8 TP24 TP21 R44 C126 C68 R59 C158 L1 C156 C106 R27 J3 C25 R88 C51 TP4 C80 C125 R40 C41 J8 C75 C47 C66 Q3 R82 J6 R84 C45 R28 C79 TP26 C113 C137 C170 C69 C34 R85 C101 C86 C168 J2 U9 R38 C33 C130 R83 C63 C98 C19 C9 R34 R32 C36 R33 D4 C166 U10 C147 C165 C76 L2 R29 R16 C40 C148 C49 RN10 C30 C8 C65 Q5 R30 RN11 C64 R67 C71 C90 C169 D1 R50 C123 C78 J17 R22 C124 C82 TP22 C...

Page 97: ...03 36 JA 002 43 JTAG Interface 41 JTAG Emulator Adapter 43 N NAND Flash 33 34 O Operating Temperature 46 Operating Voltage 46 P phyCORE connector 7 8 Physical Dimensions 45 Pin Description 7 Pinout 9 Power Consumption 46 R RS 232 Interface 37 RS 232 Level 37 RS 232 Transceiver 37 RTC 29 S SDR SDRAM 33 34 SDRAM 33 34 SMT Connector 7 Storage Temperature 46 System Configuration 31 System Memory 33 T ...

Page 98: ...yCOREi MX27 90 PHYTEC Messtechnik GmbH 2011 L 710e_5 U600 34 U601 35 U602 33 34 U603 33 34 UART3 37 UART5 37 USB Device 39 USB Host 39 USB On The Go 39 USB OTG 39 USB Transceiver 39 W Weight 46 X X201 41 ...

Page 99: ...CORE i MX27 Document number L 710e_5 February 2011 How would you improve this manual Did you find any mistakes in this manual page Submitted by Customer number Name Company Address Return to PHYTEC Technologie Holding AG Postfach 100403 D 55135 Mainz Germany Fax 49 6131 9221 33 ...

Page 100: ...Published by PHYTEC Messtechnik GmbH 2011 Ordering No L 710e_5 Printed in Germany ...

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