Jumper Layout
PHYTEC Meßtechnik GmbH 2000 L-525e_2
17
3.1
BDM interface JP1, JP2, JP5 to JP9, JP17
Jumper
Default
Description
JP1
JP1 connects the BDM reset signal to one of the
target reset signals.
1+2
BDM reset signal to /PORESET
3+4
X
BDM reset signal to /HRESIN
5+6
BDM reset signal to /HRESET
7+8
BDM reset signal to /SRESET
JP2
Selection of the signal interface voltage to the
target-processor BDM interface.
1+2
X
Select 3,3V BDM I/O voltage
2+3
Select 5V BDM I/O voltage
JP5
closed
X
JP5 connects the DSDI output signal of BDM
logic to the target DSDI signal.
JP6
JP6 connects the DSCK output signal of BDM
logic to the target DSCK signal.
closed
X
The target stops always in debug mode after
RESET
open
The target runs in normal mode after RESET
JP7
closed
X
JP7 connects the VFLS0 output signal of the
target to the BDM logic.
JP8
closed
X
JP8 connects the VFLS1 output signal of the
target to the BDM logic.
JP9
closed
X
JP9 connects the DSD0 output signal of the target
to the BDM logic.
JP17
JP17 connects /HRESET or /SRESET to the
BDM interface logic. This is used to read the reset
status from the debugger.
1+2
X
/HRESET is attached to the BDM interface logic.
3+4
/SRESET is attached to the BDM interface logic.
To connect an external BDM interface via pin header X4, jumpers
JP1, JP2, JP5 to JP9 must be removed. Select the appropriated BDM
supply voltage with J17. Some BDM interfaces provide their own
power supply and do not need the supply voltage of the development
board.
