IC Data Sheets
8.
Figure 8-5 Pin configuration
19490_
3
04_1
3
041
3
.ep
s
1
3
041
3
Pinnin
g
information
PNX5
8
XXX [
3
/16]
C26
[1]
S
CL1
I/O
I2C
3
V, 5 VT, OD
I
2
C-1
S
eri
a
l Clock M
as
ter/
S
l
a
ve DMA
0
t
i
b
k
s
a
M
Q
D
y
r
o
m
e
M
a
t
a
d
2
R
D
D
O
0
M
D
_
0
M
1
D
d
n
u
o
r
g
R
W
P
S
S
V
2
D
D
3
M0_DQ
S
1_N
I/O
DDR2
s
tro
b
e
Memory DQ
S
tro
b
e
b
it 1 Neg
a
tive
D4
M0_DQ
S
1_P
I/O
DDR2
s
tro
b
e
Memory DQ
S
tro
b
e
b
it 1 Po
s
itive
1
t
i
b
k
s
a
M
Q
D
y
r
o
m
e
M
a
t
a
d
2
R
D
D
O
1
M
D
_
0
M
5
D
D6
VDD_1V
8
PWR
su
pply
D7
LOUT
3
_AN
O
LVD
S
LVD
S3
Ch
a
nnel A Neg
a
tive
D
8
LOUT
3
_BP
O
LVD
S
LVD
S3
Ch
a
nnel B Po
s
itive
D9
LOUT
3
_CN
O
LVD
S
LVD
S3
Ch
a
nnel C Neg
a
tive
D10
LOUT
3
_CLKP
O
LVD
S
LVD
S3
Clock Po
s
itive
D11
LOUT
3
_DN
O
LVD
S
LVD
S3
Ch
a
nnel D Neg
a
tive
D12
LOUT
3
_EP
O
LVD
S
LVD
S3
Ch
a
nnel E Po
s
itive
D1
3
VDDA_2V5_LVD
S
_BG
PWR
su
pply
2.5 V
Su
pply for B
a
nd G
a
p
D14
LOUT4_AN
O
LVD
S
LVD
S
4 Ch
a
nnel A Neg
a
tive
D15
LOUT4_BP
O
LVD
S
LVD
S
4 Ch
a
nnel B Po
s
itive
D16
LOUT4_CN
O
LVD
S
LVD
S
4 Ch
a
nnel C Neg
a
tive
D17
LOUT4_CLKP
O
LVD
S
LVD
S
4 Clock Po
s
itive
D1
8
LOUT4_DN
O
LVD
S
LVD
S
4 Ch
a
nnel D Neg
a
tive
D19
LOUT4_EP
O
LVD
S
LVD
S
4 Ch
a
nnel E Po
s
itive
d
n
u
o
r
g
R
W
P
S
S
V
0
2
D
D21
C
S
B_CEN1
O
CMO
S
3
.
3
V, PU
Chip En
ab
le 1
D22
ADVB
I/O
CMO
S
3
.
3
V
Memory Addre
ss
V
a
lid
D2
3
CA_D
3
I/O
CMO
S
3
.
3
V
CA D
a
t
a
B
us
Bit-
3
(I/O)
D24
CA_IOWRN
I/O
CMO
S
3
.
3
V
CA I/O Write (O
u
tp
u
t)
D25
CA_D0
I/O
CMO
S
3
.
3
V
CA D
a
t
a
B
us
Bit-0 (I/O)
D26
CA_D1
I/O
CMO
S
3
.
3
V
CA D
a
t
a
B
us
Bit-1 (I/O)
E1
M0_DQ7
I/O
DDR2 d
a
t
a
Memory D
a
t
a
b
it 7
E2
M0_DQ
S
0_N
I/O
DDR2
s
tro
b
e
Memory DQ
S
tro
b
e
b
it 0 Neg
a
tive
E
3
M0_DQ
S
0_P
I/O
DDR2
s
tro
b
e
Memory DQ
S
tro
b
e
b
it 0 Po
s
itive
E4
V
SS
PWR gro
u
nd
E5
M0_DQ10
I/O
DDR2 d
a
t
a
Memory D
a
t
a
b
it 10
E6
VDD_1V
8
PWR
su
pply
E7
LOUT
3
_AP
O
LVD
S
LVD
S3
Ch
a
nnel A Po
s
itive
E
8
LOUT
3
_BN
O
LVD
S
LVD
S3
Ch
a
nnel B Neg
a
tive
E9
LOUT
3
_CP
O
LVD
S
LVD
S3
Ch
a
nnel C Po
s
itive
E10
LOUT
3
_CLKN
O
LVD
S
LVD
S3
Clock Neg
a
tive
E11
LOUT
3
_DP
O
LVD
S
LVD
S3
Ch
a
nnel D Po
s
itive
E12
LOUT
3
_EN
O
LVD
S
LVD
S3
Ch
a
nnel E Neg
a
tive
B
a
ll
S
ym
b
ol
P
a
d
direc-
tion
P
a
d type
De
s
cription