10.
Circuit Diagrams and PWB Layouts
10-4-12
PNX85500-CONTROL
19490_515_1
3
041
3
.ep
s
1
3
070
3
PNX
8
5500-CONTROL
B05D
B05D
2012-12-21
1
3
1
3
9 2
83
3
0
3
51
PNX
8
5500-CONTROL
D
C
S
W
HOLD
V
SS
Q
VCC
S
CL
ADR
0
1
2
S
DA
WC
MAIN NVM
DEBUG ONLY
FOR
S
DA
S
CL
LEVEL
DEBUG
U
S
E ONLY
S
HIFTED
UP
DEBUG / R
S
2
3
2 INTERFACE
FF29
7
2
1
8
4
3
7F52
M25P05-AVMN6
FLA
S
H
512K
Φ
6
5
FF61
+
3
V
3
RE
S
1
2
3
4
5
6
7
1F51
FF57
FF66
100R
3
F59
3
F60
100R
IF57
9F51
100R
3
F64
FF64
10K
3
F67
3
F62
100R
FF56
FF55
RE
S
1
u
0
2F5
3
+
3
V
3
+
3
V
3
3
F54
1K0
RE
S
RE
S
IF54
10K
3
F5
3
FF65
FF0
3
100R
3
F65
FF2
8
10K
3
F69
RE
S
10K
3
F66
FF6
3
RE
S
3
F5
8
10K
FF04
IF55
2F49
100p
+
3
V
3
-
S
TANDBY
10K
3
F52
+
3
V
3
-
S
TANDBY
FF5
8
IF56
+
3
V
3
-
S
TANDBY
IF59
FF62
4
+
3
V
3
-
S
TANDBY
7F54-2
BC
8
47BPN(COL)
5
3
2
6
1
RE
S
+
3
V
3
RE
S
7F54-1
BC
8
47BPN(COL)
47K
3
F6
8
RE
S
PDTA114EU
7F5
3
RE
S
4
5
100R
3
F6
3
RE
S
1
2
3
1F52
2F5
8
100n
2
3
6
5
8
4
7
RE
S
7F5
8
(
8
Kx
8
)
1
Φ
EEPROM
+5V
RE
S
100n
2F52
RE
S
ET-
S
TBYn
S
PI-PROG
BL-I-CTRL-PNX
S
PI-PROG
S
DM
TXD-UP
RXD-UP
BL-I-CTRL
S
DA-UP-MIP
S
S
CL-UP-MIP
S
S
CL-
SS
B-550
S
DA-
SS
B-550
PNX-
S
PI-CLK
PNX-
S
PI-
S
DO
PNX-
S
PI-
S
DI
PNX-
S
PI-C
S
Bn
PNX-
S
PI-WPn