Philips 26HFL5008D/12, Service Manual

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IC Data Sheets EN 36 Q552.5HE LA 8.
2013-Sep-20
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div. table
Figure 8-4 Pin configuration
19490_ 3 0 3 _1 3 041 3 .ep s
1 3 041 3
Pinnin g information
PNX5 8 XXX [2/16]
B1 3 VDDA_1V15_LVD S _PLL PWR LVD S 1.1 V An a log Su pply for PLL
B14 LOUT2_AP O LVD S LVD S 2 Ch a nnel A Po s itive
B15 LOUT2_BP O LVD S LVD S 2 Ch a nnel B Po s itive
B16 LOUT2_CP O LVD S LVD S 2 Ch a nnel C Po s itive
B17 LOUT2_CLKP O LVD S LVD S 2 Clock Po s itive
B1 8 LOUT2_DP O LVD S LVD S 2 Ch a nnel D Po s itive
B19 LOUT2_EP O LVD S LVD S 2 Ch a nnel E Po s itive
B20 V SS PWR gro u nd
B21 CLK_BUR S T I/O CMO S 3 . 3 V, PU Fl as h Memory Clock
B22 CA_OEN I/O CMO S 3 . 3 V CA O u tp u t En ab le (O u tp u t)
B2 3 CA_D5 I/O CMO S 3 . 3 V CA D a t a B us Bit-5 (I/O)
B24 S DA4 I/O I2C 3 V, 5 VT, OD I
2
C-4 S eri a l D a t a M as ter/ S l a ve DMA
I D O , T V 5 , V 3 C 2 I O / I 3 A D S 5 2 B
2
C- 3 S eri a l D a t a M as ter/ S l a ve DMA
I D O , T V 5 , V 3 C 2 I O / I 2 A D S 6 2 B
2
C-2 S eri a l D a t a M as ter/ S l a ve DMA
C1 M0_DQ6 I/O DDR2 d a t a Memory D a t a b it 6
C2 M0_DQ1 I/O DDR2 d a t a Memory D a t a b it 1
C 3 M0_DQ 3 I/O DDR2 d a t a Memory D a t a b it 3
d n u o r g R W P S S V 4 C
C5 M0_DQ11 I/O DDR2 d a t a Memory D a t a b it 11
C6 VDD_1V 8 PWR su pply
C7 VDD_2V5_LVD S PWR su pply 2.5 V Su pply for LVD S Phy
C 8 LOUT1_BN O LVD S LVD S 1 Ch a nnel B Neg a tive
C9 VDD_2V5_LVD S PWR su pply 2.5 V Su pply for LVD S Phy
C10 LOUT1_CLKN O LVD S LVD S 1 Clock Neg a tive
C11 VDD_2V5_LVD S PWR su pply 2.5 V Su pply for LVD S Phy
C12 LOUT1_EN O LVD S LVD S 1 Ch a nnel E Neg a tive
C1 3 V SS A_2V5_LVD S _BG PWR gro u nd Gro u nd Su pply for BG
C14 VDD_2V5_LVD S PWR su pply 2.5 V Su pply for LVD S Phy
C15 LOUT2_BN O LVD S LVD S 2 Ch a nnel B Neg a tive
C16 VDD_2V5_LVD S PWR su pply 2.5 V Su pply for LVD S Phy
C17 LOUT2_CLKN O LVD S LVD S 2 Clock Neg a tive
C1 8 VDD_2V5_LVD S PWR su pply 2.5 V Su pply for LVD S Phy
C19 LOUT2_EN O LVD S LVD S 2 Ch a nnel E Neg a tive
d n u o r g R W P S S V 0 2 C
t s r u B e c n a v d A s s e r d d A y r o m e M U P , V 3 . 3 S O M C O B A A B 1 2 C
C22
CA_WEN I/O CMO S 3 . 3 V CA Write En ab le (O u tp u t)
C2 3 CA_D4 I/O CMO S 3 . 3 V CA D a t a B us Bit-4 (I/O)
C24 CA_D2 I/O CMO S 3 . 3 V CA D a t a B us Bit-2 (I/O)
C25 S DA1 I/O I2C 3 V, 5 VT, OD I
2
C-1 S eri a l D a t a M as ter/ S l a ve DMA
B a ll S ym b ol P a d
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