IC Data Sheets
8.
Figure 8-3 Pin configuration
19490_
3
02_1
3
041
3
.ep
s
1
3
041
3
Pinnin
g
information
PNX5
8
XXX [1/16]
B
a
ll
S
ym
b
ol
P
a
d
direc-
tion
P
a
d type
De
s
cription
d
n
u
o
r
g
R
W
P
S
S
V
1
A
A2
M0_VREF_1
I
a
n
a
log
Memory Volt
a
ge Reference Inp
u
t 1
d
n
u
o
r
g
R
W
P
S
S
V
3
A
A4
M0_DQ12
I/O
DDR2 d
a
t
a
Memory D
a
t
a
b
it 12
A5
VDD_1V
8
PWR
su
pply
A6
VDD_1V
8
PWR
su
pply
A7
LOUT1_AN
O
LVD
S
LVD
S
1 Ch
a
nnel A Neg
a
tive
d
n
u
o
r
g
R
W
P
S
S
V
8
A
A9
LOUT1_CN
O
LVD
S
LVD
S
1 Ch
a
nnel C Neg
a
tive
d
n
u
o
r
g
R
W
P
S
S
V
0
1
A
A11
LOUT1_DN
O
LVD
S
LVD
S
1 Ch
a
nnel D Neg
a
tive
d
n
u
o
r
g
R
W
P
S
S
V
2
1
A
A1
3
V
SS
A_1V15_LVD
S
_PLL
PWR LVD
S
Gro
u
nd
Su
pply for PLL
A14
LOUT2_AN
O
LVD
S
LVD
S
2 Ch
a
nnel A Neg
a
tive
d
n
u
o
r
g
R
W
P
S
S
V
5
1
A
A16
LOUT2_CN
O
LVD
S
LVD
S
2 Ch
a
nnel C Neg
a
tive
d
n
u
o
r
g
R
W
P
S
S
V
7
1
A
A1
8
LOUT2_DN
O
LVD
S
LVD
S
2 Ch
a
nnel D Neg
a
tive
d
n
u
o
r
g
R
W
P
S
S
V
9
1
A
1
y
d
a
e
R
y
r
o
m
e
M
D
P
,
V
3
.
3
S
O
M
C
I
1
N
B
_
R
0
2
A
n
o
i
t
c
e
t
o
r
P
e
t
i
r
W
h
s
a
l
F
d
n
a
N
V
3
.
3
S
O
M
C
O
/
I
0
N
P
W
1
2
A
A22
CA_D6
I/O
CMO
S
3
.
3
V
CA D
a
t
a
B
us
Bit-6 (I/O)
A2
3
S
CL4
I/O
I2C
3
V, 5 VT, OD
I
2
C-4
S
eri
a
l Clock M
as
ter/
S
l
a
ve DMA
I
D
O
,
T
V
5
,
V
3
C
2
I
O
/
I
3
L
C
S
4
2
A
2
C-
3
S
eri
a
l Clock M
as
ter/
S
l
a
ve DMA
I
D
O
,
T
V
5
,
V
3
C
2
I
O
/
I
2
L
C
S
5
2
A
2
C-2
S
eri
a
l Clock M
as
ter/
S
l
a
ve DMA
d
n
u
o
r
g
R
W
P
S
S
V
6
2
A
d
n
u
o
r
g
R
W
P
S
S
V
1
B
B2
M0_DQ9
I/O
DDR2 d
a
t
a
Memory D
a
t
a
b
it 9
B
3
M0_DQ14
I/O
DDR2 d
a
t
a
Memory D
a
t
a
b
it 14
B4
M0_DQ4
I/O
DDR2 d
a
t
a
Memory D
a
t
a
b
it 4
B5
VDD_1V
8
PWR
su
pply
B6
VDD_1V
8
PWR
su
pply
B7
LOUT1_AP
O
LVD
S
LVD
S
1 Ch
a
nnel A Po
s
itive
B
8
LOUT1_BP
O
LVD
S
LVD
S
1 Ch
a
nnel B Po
s
itive
B9
LOUT1_CP
O
LVD
S
LVD
S
1 Ch
a
nnel C Po
s
itive
B10
LOUT1_CLKP
O
LVD
S
LVD
S
1 Clock Po
s
itive
B11
LOUT1_DP
O
LVD
S
LVD
S
1 Ch
a
nnel D Po
s
itive
B12
LOUT1_EP
O
LVD
S
LVD
S
1 Ch
a
nnel E Po
s
itive