Circuit Descriptions
7.
7.
Circuit Descriptions
Index of this chapter:
7.1 Introduction
7.2 Power Supply
Notes:
•
Only
new
circuits (circuits that are not published recently)
are described.
•
Figures can deviate slightly from the actual situation, due
to different set executions.
•
For a good understanding of the following circuit
descriptions, please use the wiring, block (see chapter
) and circuit diagrams (see chapter
10. Circuit Diagrams and PWB Layouts
).Where necessary,
you will find a separate drawing for clarification.
7.1
Introduction
The Q552.5HE LA is part of the TV550 “R4” 2012 platform and
is a derivative from the Q552.4E LA.
7.1.1
Implementation
Key components of this chassis are:
•
PNX855xx System-On-Chip (SOC) TV Processor
•
SUT-RE214Z Hybrid Tuner (DVB-T/C, analogue)
•
STV6110A DVB-S Satellite Tuner
•
SII9x87 HDMI Switch
•
TAS5731 Class D Power Amplifier
•
LAN8710 Dual Port Gigabit Ethernet media access
controller.
7.1.2
TV550 Architecture Overview
For details about the chassis block diagrams refer to
chapter 9.
. An overview of the TV550 “R4” 2012
architecture can be found in
.
Figure 7-1 Architecture of TV550 R4 platform - Hotel range (5008 series)
19220_017_120224.ep
s
120224
Cell
FHD@120
AL
PNX
8
5500
NR
DEI
PQ Enh
a
ncement
FRC
3
D: Active
I
2
S
2 × LVD
S
for 4000
s
4 × LVD
S
for 5000
s
/5500
s
PWM
Temp
S
en
s
or
3
D
a
ctive
8
x PWM
Temp
S
en
s
or
S
hop
I
2
C/An
a
log
CLA
SS
-D
3
D-IR
PWM: temp. ctrl Gl
ass
BL
A
u
dio
AL mod
s
.
S
PI
B
a
cklight
3
D goggle drive
Am
b
ilight CPLD
FPGA
S
p
a
rt
a
n 6
LX4
Am
b
ilight CPLD
BOO
S
T
HDMI
92
8
7
Hy
b
rid
T
u
ner
DVB
T2
DVB-
S
2
T
u
ner
DVB
S
2
3
2
DDR 512 MB
4 × 1 G
b
(×
8
)
FLA
S
H
512 MB
CI+
ETH
PHY
U
S
B
HUB
Not Applic
ab
le
for 5000
s
erie
s
∗
∗
S
erie
s
su
pply volt
a
ge
40x7
24 V
4
3
x7
12 V
50x7
12 V
Cl
ass
D Amplifier