Panasonic KX-HCM280, Service Manual

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Receiving Operation
1. After receiving one packet of data, the LAN controller informs the
CPU of it.
2. The CPU checks if the packet is normal.
3. If normal, the CPU transfers the data on the Receive Buffer to the
data port, using the Remote DMA. If abnormal (error), the CPU
abandons the packet.
4. The CPU reads receive data out of the data port.
14.1.3. Video Decoder & JPEG Block
VIDEO DECODER (IC601)
Operating Power Supply: +3.3V
Package: 100 pin QFP
Operating Clock: 24.54MHz
The video decoder (IC601) converts the analog video signal output from the camera unit into the
digital signal in real time. It converts each analog signal of Y/C into 8 bit *2 digital signal of Y/UV.
JPEG CODEC (IC701)
Operating Power Supply: +3.3V
Package: 100 pin QFP
Operating Clock: 16.67MHz
Captures digital image data (saves the data in the IC702 DRAM for JPEG), and compresses it in
JPEG format. The compressed data is stored in the SDRAM (IC103) by the DMAC incorporated in
the CPU.
DRAM (IC702)
Operating Power Supply: +3.3V
Package: 44 pin TSOP
Capacity: 4Mbit
Access Time: 60ns
Used for capturing and compressing JPEG images.
Image Data Flow
1. The analog Y/C signal is sent to the video decoder from the
camera unit.
2. The above data is converted into 8 bit Y data and 8 bit UV data with
the video decoder (IC601), and then sent to VIDEO-I/F of JPEG
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