Panasonic EURO 4 Chassis Technical Manual Download Page 86 | Manualshive

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3DQDVRQLF

3

Introduction

We at Panasonic realise that the service engineer
needs to understand the circuitry inside the TV and for
this need, we have produced this Supplemental
Technical Guide.

This Supplemental Technical Guide contains updated
information for the following:

:

EURO 4 chassis.

:

EURO 4H chassis with new simple 100Hz
processing.

:

EURO 4D IDTV chassis with integrated Digital
Video Broadcasting (DVB) terrestial decoder.

This supplemental technical guide should be used
in-conjunction with the EURO 4 Technical Guide and
the relevant Service Manuals.

Only those differences which have arisen with the
introduction of new models are covered in this
Supplemental Technical Guide, all other information
is as presented in the EURO 4 Technical Guide
(TZS8EL001).

As this supplemental technical guide covers three
variants of the EURO 4 chassis, this technical guide
has been split into chapters as presented in the
contents.

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Summary of Contents for EURO 4 Chassis

Page 1: ...Order No TZS8EL001 Technical Guide Colour Television EURO 4 Chassis Circuit Explanations 3DQDVRQLF XURSHDQ 7HOHYLVLRQ LYLVLRQ 0DWVXVKLWD OHFWULF 8 WG ...

Page 2: ... F Output Stage 21 11 Colour Output Stage 22 12 RF IF Section 25 13 Microprocessor and Teletext Processing 27 14 EAROM Memory IC 37 15 EPROM 38 16 Control Of The Digital Section 39 17 Video Display Processor 40 18 M Board Processing 55 19 AV Switching 57 20 Audio Signal Processing 58 21 History Of Dolby Pro Logic 67 22 Pro Logic Processing Overview 68 23 Pro Logic Encoding and Decoding Concepts 69...

Page 3: ... Technical Guide contains information for EURO 4 chassis and should be used in conjunction with the relevant Service Manuals for this chassis As the Technical Guide for the Euro 4 chassis covers such a wide range of models some differences occur in circuit descriptions and component reference numbers Where these differences occur they will be highlighted by Italic text with brackets ...

Page 4: ...62 R854 33V REMOTE CONTROL RECEIVER RESET MICRO PROCESSOR Audio Processor Video Processor EPROM EAROM RESET REG REG REG 7 Video Switching EW CORRECTION POWER SUPPLY RGB V OUTPUT AUDIO OUTPUT D801 E BOARD Y BOARD E8 1 Y2 1 N1 2 E19 2 E1 4 1 E2 2 1 R802 DEGAUSS COIL Line Filter E62 1 2 4 IC2404 8 IC2403 1 3 3 5 6 1 4 IC2401 4 IC2702 3 5 3 5 3 5 S S F P 18V 18V T2701 P 3 R2714 Q2702 Q2701 R2715 S 22V...

Page 5: ...IC1071 81 AV2 8 10 AV1 8 10 12 75 51 72 73 AV LINK SLOW 2 SLOW 1 SCL 1 SDA 1 58 59 55 VPROT KEYSCAN R C L E D PROT 1 SLOW 2 OUT IN SLOW 1 SERVICE SCL SDA H BOARD E BOARD VIDEO SWITCHING AUDIO PROCESSOR MICROPROCESSOR VIDEO PROCESSOR EAROM REMOTE CONTROL RECEIVER N BOARD 8 8 IC2401 7 8 K2 3 E11 3 4 4 K BOARD IC1051 REMOTE CONTROL RECEIVER Model Specific 3 CONTROL BLOCK DIAGRAM 5 3DQDVRQLF Dolby Pro...

Page 6: ... 3 5 Q353 CRT 3 2 1 7 8 9 Y2 4 3 5 IC351 Q104 5HG OXH UHHQ 9LGHR Q 9 9LGHR 2XW G OUT 38 R OUT 37 G IN 46 R IN 45 Q30 Q302 7 7 VM COILS Q905 Q907 Q909 Q908 Q906 SVM OUT 34 Q950 Q951 Q3001 G 38 B 39 Y BOARD E BOARD RGB OUTPUT VIDEO PROCESSOR MICRO PROCESSOR H3 E61 E15 1 6 8 H1 1 6 8 IC3401 Q3402 Q3401 8 6 5 H BOARD VIDEO SWITCHING Model Specific 4 VIDEO BLOCK DIAGRAM 6 3DQDVRQLF ...

Page 7: ... IN 47 ANA_IN1 44 MONO IN DACM_L 25 SC3_IN_R 38 SC1_IN_R 42 SC1_IN_L 41 SC2_OUT_R 27 SC2_OUT_L 28 SC2_IN_R 40 SC2_IN_L 39 Q252 Q251 2 L L 11 4 L HEADPHONE 7 R 5 L E6 1 E7 3 Q2304 Q2302 21 DACA_R 22 DACA_L E BOARD AUDIO PROCESSOR AUDIO OUTPUT AUDIO MONITOR OUT Q2303 Q2301 49 ANA_IN2 Q103 X101 X102 Model Specific Model Specific 5 STANDARD AUDIO BLOCK DIAGRAM 7 3DQDVRQLF ...

Page 8: ...A_IN1 44 MONO IN DACM_L 25 SC3_IN_R 38 SC1_IN_R 42 SC1_IN_L 41 SC2_OUT_R 27 SC2_OUT_L 28 SC2_IN_R 40 SC2_IN_L 38 Q252 Q251 2 L L 11 HEADPHONE 2 R 3 L Q2304 Q2302 21 DACA_R 22 DACA_L E12 3 4 5 6 7 I2S_DA_IN_2 18 I2S_DA_IN_1 12 I2S_DA_OUT 11 I2S_DA_WS 10 I2S_DA_CL 9 I2S_DA_IN_2 I2S_DA_IN_1 I2S_DA_OUT I2S_DA_WS I2S_DA_CL E23 3 1 To K3 From K8 H_LEFT H_RIGHT R L E BOARD Model Specific Model Specific 6...

Page 9: ... 5 7 IC2704 IC2703 IC2702 K6 1 JK2402 Q2410 Q2409 1 1 1 4 4 4 Audio Left Audio Right Headphone Left Headphone Right Surround Centre Woofer Surround L Centre Surround R Woofer Surround L Centre Out Left Front Surround R Right Front Q2427 Q2424 Q2423 Q2422 Q2419 Q2418 Q2417 Q2421 Q2420 I2S_DAOUT_2 I2S_DA_OUT_1 I2S_DA_IN 6 7 10 9 I2S_WS I2S_CL Q2704 Q2703 Q2705 C Board K Board 7 DOLBY BLOCK DIAGRAM 9...

Page 10: ...s the A C supply being fed to the normally open contact of the standby relay RL801 The second path has the A C supply being fed via the windings P1 P2 of the standby transformer T802 8 1 Standby Power Supply Circuit The standby transformer T802 has the A C supply as just mentioned being fed via the primary winding P2 P1 From the output of the secondary windings S2 S1 of the standby transformer a 5...

Page 11: ...D871 this supply being used to reduce the load on the standby transformer when the TV is in normal operation The second path is via resistor R862 to the base of transistor Q852 This supply being regulated by the zener diode D872 is used as a base bias 2 The second path from the standby transformer T802 that the supply voltage follows is via the rectifying diode D867 and smoothing capacitor C871 He...

Page 12: ...hich with altered operation in standby mode allows the supply to fulfil both power on and standby roles The IC features pulse by pulse overcurrent protection over voltage protection with latch and thermal protection functions 8 2 1 General The mains voltage flows through the mains suppression filter and standby relay before being fed via the bridge rectifier D801 and transformer T801 primary windi...

Page 13: ...drive the internal MOS FET transistor into conduction resulting in current flow via the primary winding pin 3 drain terminal and pin 2 source terminal of IC801 Once IC801 begins to operate the supply voltage at pin 4 is supplied via the rectifying diode D803 and smoothing capacitor C816 which is fed from the drive winding of the switching transformer T801 This supply voltage which is fed from the ...

Page 14: ...ary winding P2 P1 stops This results in the collapse of the magnetic field and the energy stored in the primary winding is transferred to the secondary windings During this period the voltage at pin 1 of IC801 begins to fall at a rate determined by C819 When the internal comparator of IC801 detects that the voltage at pin 1 is below the internally generated 0 73V reference signal the MOS FET is sw...

Page 15: ...creases until the the Vcc input reaches the shut down voltage of 10V At this point pin 4 begins to rise again but when it reaches the start up level 16V the latch circuit continues to stop the drive When the latch is ON Vcc pin 4 voltage increases and decreases within the 10V to 16V range as shown in the above fig and is prevented from rising normally Cancellation of the latch is achieved by switc...

Page 16: ...tage 8 7 1 Voltage Stabilisation The stabilisation of the previously mentioned secondary supplies is performed as follows A 15V supply which is fed from the transformer T801 is fed to pin 1 of IC851 which is used to produce a stabilized 12V supply This supply is then also used to produce the 9V Wide Screen Models ONLY and 8V supplies The wide screen models which use a 9V supply is produced by feed...

Page 17: ...the driver of the line output stage it can be clearly seen that this is low impedance current control The driver stage is fitted with a transistor which is able to supply the necessary base control current of up to 0 9 Amps for the driver transformer T501 of the output stage To limit the inductive breaking peaks during the blocking phase the RC combination R509 R510 C511 are connected in parallel ...

Page 18: ... specially for dual utilisation of Q551 in normal and inverse mode In principle the pulse duty factor of the base drive has been altered from 12mS flyback time and 52mS sweep time to 20mS flyback time and 44mS sweep time Thus it is also possible to process any unavoidable delays in the driver transformer As a result of prompt driving the switching transistor has adequate preparation for the subseq...

Page 19: ...lator D551 D552 Output from the VDP IC601 pin 32 a parabola waveform of 1v pp occurs which is passed via R847 to buffer transistor Q701 before being input via pin 7 of the East West IC IC701 Here the parabola waveform is fed to a comparator where the parabola waveform is compared with the horizontal flyback pulse from the output of the comparator the E W drive signal is output via pin 5 and fed to...

Page 20: ... top left corner of the screen This brief additional energy requirement is met by doubling the supply voltage available to the output stage During vertical sweep the bootstrap capacitor C456 is charged up to almost supply voltage via D454 The output of the pump up generator pin 7 IC451 is at this moment at ground potential As a result of the DC displacement at the negative pole of capacitor C456 r...

Page 21: ...active mute circuit is used in parallel to the inputs of the audio output IC IC251 This active mute circuit consists of two transistors Q251 and Q252 which is controlled by transistor Q2101 Transistor Q2101 is used to prevent POP during switch ON and OFF times The POP mute circuit is fed a 5V supply and a12V supply The 5V supply which is fed via diode D2102 charges up capacitor C2129 while the 12V...

Page 22: ...oils Transistors Q906 and Q907 are connected as impedance converters which control the output stage at low impedance without distortion Transistors Q908 and Q909 then outputs the signal at approximately 35Vpp via connector Y6 pins 1 and 3 to the SVM coils the scan coils being controlled directly from the collector terminals of transistors Q908 and Q909 via resistor R929 which is coupled in paralle...

Page 23: ...ses transistor Q552 switches OFF this means that resistor R564 is no longer in parallel with R262 R263 thus reducing the above mentioned artifacts 0 855 17 0 7 7 21 7KH PHDVXUHPHQW RI WKH EHDP FXUUHQW DV PHQWLRQHG LQ WKH SUHYLRXV VHFWLRQ LV IHG YLD WKH 6HQVH LQSXW RI WKH 9 3 SLQ WKH UHVXOW RI WKH PHDVXUHPHQW EHLQJ FRPSDUHG WR WKH YDOXH VWRUHG LQ PHPRU 7KH UHVXOW RI ZKLFK LV XVHG WR UHGXFH WKH GULY...

Page 24: ...3DQDVRQLF 24 ...

Page 25: ...t the tuning range 2 Excessively limit the efficiency of the circuit operation Because of the above drawbacks each band has its own bias stage correction circuits and band filter with optimised tuning diodes Each part tuner can thus be biased and set for its frequency range The IF stage of the combi tuner contains the video and audio demodulators which are designed for the most widely used TV stan...

Page 26: ...3DQDVRQLF 26 TV STANDARDS ...

Page 27: ...mote control decoding Serial Interface 256 bytes on chip RAM 10kbytes on chip display RAM 1 kbyte on chip ACQ buffer RAM 1 kbyte on chip extended RAM 6 channel 8 bit pulse Width Modulator 2 channel 14 bit Pulse Width Modulator 4 multiplexed ADC inputs with 8 bit resolution One 8 bit In Out port with open drain and operational I2C bus emulation Two 8 bit multifunctional In Out ports One 4 bit port ...

Page 28: ... from standby the required operational data is reload back into the VDP IC601 and MSP IC2101 This is achieved with reset IC IC1105 which monitors the 5V supply line via pin 2 When the 5V supply falls to approximately 4 3V the reset IC IC1105 inputs a reset pulse via pin 54 of the microprocessor IC1101 Pin 58 Slow1 Pin 59 Slow2 The circuit is designed so that it is possible to switch over to AV ope...

Page 29: ...ter is used by the teletext slicer Pin 67 IRef This is a reference current for internal PLL Pin 68 CVBS In This composite video signal which is input via pin 68 is used for teletext processing which is carried out within the microprocessor IC1101 Pin 71 VProt This input is used to detect a fault in the deflection circuit Where there are no errors a HIGH level is applied to the base of Q451 which r...

Page 30: ...RU 5 Q WKLV VWDWH WKH SURWHFWLRQ FLUFXLW GRHV QRW RSHUDWH KHUH DQ HUURU GHVFULEHG DULVHV DQG WKH EHDP FXUUHQW FRQWLQXHV WR ULVH WKHQ WKH HQHU GLRGH FRQGXFWV GXH WR WKH QHJDWLYH YROWDJH IHG EDFN IURP 7 O EDFN WUDQVIRUPHU ZKLFK FDXVHV GLRGH WR FRQGXFW SXOOLQJ WKH DQRGH RI WKH HQHU GLRGH ORZHU WKDQ LWV FDWKRGH V LWV DQRGH LV SXOOHG ORZHU LWV FDWKRGH EHFRPHV PRUH SRVLWLYH 2QFH WKH HQHU GLRGHV EUHDNRYH...

Page 31: ...from pin 53 of the microprocessor IC1101 During switch ON the digital ICs are held LOW by Q1101 which is conducting at this point due to the 5V standby supply fed to the base of Q1101 via R1112 Once the supply voltages have become established pin 53 of the microprocessor IC1101 pulls the base of Q1101 LOW resulting in it switching OFF a HIGH level is then fed via R1111 to the digital ICs initiatin...

Page 32: ...nd AV2 Pin 81 LED The standby LED D1071 located on the N Board D1061 located on the M Board is controlled via pin 81 of the microprocessor IC1101 In standby mode the pin is set to a HIGH level which causes Q1052 on the E Board Q1062 on the M Board to switch ON causing the standby LED to light up Pin 81 is also used to flash the standby LED when the Infra red remote control receiver receives a sign...

Page 33: ...n control information fed via the AV_Link is as follows TV Auto Power ON TV automatically turns ON when the VCR starts play back VCR Auto Standby VCR will automatically switch to standby when the TV is turned OFF unless the VCR is in recording mode TV On screen Display of VCR status Down load of Country selection These above features will only work with a Panasonic TV video combination who are bot...

Page 34: ...5HFHLYHU 7UDQVPLWWHU 6ODYH 5HFHLYHU 6ODYH 7UDQVPLWWHU 5HFHLYHU 0DVWHU 7UDQVPLWWHU 6ODYH 7UDQVPLWWHU 5HFHLYHU 6 6 8 LVSOD 5 0 QWHUIDFH 8 6 IURP 0DVWHU 6WDUW 6 VLJQDO E WUDQVPLWWHU 6 VLJQDO E UHFHLYHU 6 WK ORFN LW RU 7KH EXV V VWHPV DUH JHQHUDWHG E WKH PLFURSURFHVVRU ZLWK GDWD OLQH 6 EHLQJ RXWSXW YLD SLQ DQG 6 RXWSXW YLD SLQ ZKLOH WKH UHTXLUHG FORFN OLQHV 6 DQG 6 DUH RXWSXW IURP SLQV DQG FRQVHFXWLYH...

Page 35: ...h the Teletext TTX and Video Programme Signal VPS The VPS feature is not used Display Timing which is used to ensure that the text information is locked to the same timing as the raster scan Character ROM which provides the required characters for display of text information on screen Display Generator used to create the Text display DSWXUH DWFKGRJ 7LPHU RPSDUH 7LPHU 3 0 77 936 6OLFHU FTXLVLWLRQ L...

Page 36: ... text data is then fed via the dual port interface to the buffer where under the control of the internal CPU the data is stored in the display RAM until the TTX data is required When the TTX data is requested the information is read out of the Display RAM via the interface and fed to the Display Generator The display generator then selects the pixel information from the character ROM and translate...

Page 37: ...or reading out The address word is checked for compatibility with the address contained in the IC and acknowledged by an acknowledgement bit The memory location address is then transmitted by the master I C in this case the microprocessor This address also consists of an 8 bit word whose reception is again confirmed by an acknowledgement bit If this is the case the 8 data bits are then transmitted...

Page 38: ...a memory capacity of 2Mbits the data transfer from the EPROM IC1102 to the microprocessor IC1101 being carried out via connections Q0 to Q7 The memory address from which the data will be read out is transmitted beforehand via lines A0 to A17 287387 8 56 7 1 0 75 2 5 2 5 287387 1 3 1 352 5 00 2 9FF 1 9SS 3 0 2 5 66 13876 7 2873876 ...

Page 39: ...h etc is contained in this information The customer specific tuning values such as brightness colour saturation volume etc are also included in the data The latter may be changed at any time by the customer and these changed values stored in the non volatile memory with the use of the memory function Changes to these values are transmitted to the relevant processors during the control process via ...

Page 40: ...picture improvements such as Colour Transient Improvement CTI and Scan Velocity Modulation SVM but also processing for 3 Adaptive comb filter for separation of the luma and chroma signals 4 Scaler stage which is used for wide screen models providing the required sizing of the picture for display on 16 9 CRTs VDP3112 This IC provides all the features of the VDP3120 except for the scaler stage used ...

Page 41: ...olour transient improvement RGB Processing Programmable RGB matrix digital colour bus interface additional analogue RGB fast blank input Half contrast switch Picture frame generator Deflection Scan velocity modulation output High performance H V deflection Separate ADC for tube measurements EHT compensation Miscellaneous One 20 25MHz crystal Embedded RISC controller 80 MIPS I2C Bus Interface Singl...

Page 42: ... fed from AV1 pin 20 The Input via pin 63 Vin3 is the input for the video signal fed from AV2 pin 20 or the Luminance input from an S VHS source which may be fed from AV2 pin 20 The Input via pin 64 Vin4 is the input for the video signal fed via the RCA input of AV3 Wide Screen Models ONLY or the Luminance input from the S VHS 4 pin input of AV3 Wide Screen Models ONLY The input signals mentioned ...

Page 43: ...ifier is adjusted accordingly The amplifier having a range of 6dB 4 5dB The S VHS chroma signal however is fed via a buffer amplifier with an attenuation of 1 6dB From the output of the amplifiers the video luminance and chroma signals are fed to the A D converters where the signals with a clock rate of 20 25Mhz are converted from analogue to digital form The digital video luma signal is output fr...

Page 44: ...he luminance resolution is limited about 3 8 MHz The comb filter also reduces interferences like cross luminance and cross colour artifacts without introducing new artifacts or noise Where an S VHS signal or SECAM signal is input then the comb filter is switched off in this case the signals are fed via the delay lines directly to the Colour decoder stage This also applies where the comb filter is ...

Page 45: ... 2 format 17 5 1 Digitised Composite Video Processing The video signal which is fed to the colour decoder section as 8 bits of information is split into 2 paths 1 Luminance Processing 2 Chrominance Processing 17 5 2 Luminance Processing The composite video signal is fed to a programmable notch filter which filters out the colour information The position of the filter centre frequency depends on th...

Page 46: ...n the PAL NTSC system the burst is the reference for the colour signal The phase and magnitude of the colour burst signal being used as a control pulse for the APC circuit colour killer circuit and the automatic colour control ACC stage which has a control range of 30 to 6dB During SECAM decoding the frequency of the burst is measured thus the chroma carrier frequency can be identified and used to...

Page 47: ...erscan borders distorted no cropping Panorama 4 3 4 3 non linear zoom letterbox source PAL displayed on a 4 3 tube vertical overscan borders distorted no cropping The scaler itself contains a programmable decimation filter a 1 line delay FIFO memory and a programmable interpolation filter The controlling of the scaler being performed by the internal Fast Processor 17 6 3 Black Line Detector When a...

Page 48: ...d brightness levels which would in turn cause the beam current to increase causing the CRT to overheat and produce colouration Once the signal has been output from the soft limiter the luma signal is fed to the matrix circuit for production of the RGB signals In the chrominance processing path the CrCb signals are converted from 10 125MHz to 20 25MHz sampling rate by the interpolator stage before ...

Page 49: ...om the Display processor previously explained and input to the Analogue Back End Here the digital RGB signal is converted to analogue RGB before being output from the VDP IC601 The digital RGB signal is converted to analogue using 3 digital to analogue converters DAC with 10 bit resolution here an analogue brightness value is added to the RGB signal The brightness value having an adjustment range ...

Page 50: ... L J K W Z K L W H G U L Y H 5 ELW EODQNLQJ ELW Z K L W H G U L Y H 5 NH H W F R Q W U D V W E H D P F X U U H Q W O L P L W FODPS PX ELW H W F R Q W U D V W E H D P F X U U H Q W O L P L W ELW ELW H W E U L J K W ELW H W E U L J K W ELW Z K L W H G U L Y H Z K L W H G U L Y H EODQN PHDVXUHPHQW WLPLQJ ELW PHDVXUHPHQW P H D V X U H E X I I H U H W FRQWUDVW H W EULJKWQHVV ELW EODQNLQJ ELW EODQNLQJ D...

Page 51: ...d by pins 26 and 27 of the VDP IC601 During cut off measurement the input range of the measuring A D converter is set by resistor R658 However as the white drive measurement contains alarger current range resistor R607 has also to be switched into the measurement A D converter input as well as R658 thus keeping the measured value in the range of the A D converter This information then passes via t...

Page 52: ...easuring circuit while the third path is fed to the vertical sync separation circuit 1 The 1st path feeds the sliced sync signal to the horizontal sync separator before being fed to the phase comparator and lowpass filter here the sync phase error signal is filtered under the control of the fast processor All timing in the front end is derived from the counter which is also part of the PLL1 The co...

Page 53: ...601 2 PLL3 is used to adjust the phase of the horizontal drive pulse which compensates for the delay of the horizontal output stage the horizontal output being fed via pin 50 of IC601 The horizontal drive circuitry uses a digital sine wave generator to produce an exact subclock timing for the drive pulses The generator which runs at 1MHz in the output stage divides down this frequency to produce t...

Page 54: ...ion input is used to prevent the picture tube from damage in the event of a malfunction of the vertical deflection stage During vertical blanking a signal of 2 5V is sensed If a negative edge cannot be detected the RGB output signals are blanked 2 The main oscillator and horizontal drive circuitry are run from a separate standby power supply which ensures the main oscillator and horizontal drive c...

Page 55: ...ed the audio signals are also input via AV3 and two RCA sockets These left and right audio signals are also input via AV3 and the two RCA sockets These left and right audio signals are then fed to the E Board via connectors M2 pins 8 and 10 and E17 Once the left and right audio signals are input onto the E Board the audio signals are fed directly to the MSP3410 IC2101 The M Board also contains the...

Page 56: ...nce signal from AV3 is then fed via buffer transistor Q3205 and amplifier transistor Q3206 under the control of the mix switch control which is fed from the microprocessor IC1101 pin 78 When the mix switch control is HIGH both transistors Q3205 and Q3206 conduct At the collector of Q3206 the chrominance signal follows two paths The first path that the chrominance signal follows is via Q3207 where ...

Page 57: ...V2 video out of the 21 pin scart socket Those models without the previously mentioned M Board non Wide Screen models feeds the signal selected for output via AV2 from the VDP IC601 pin 59 to connector E15 pin 6 Here the selected video signal is passed to the H Board via connector H1 pin 6 from where the video signal is fed via transistor Q3402 to pin 8 of IC3401 This video signal then follows the ...

Page 58: ...f the analogue audio signals the MSP3410D IC2101 also processes the NICAM signal fed from the I F stage 7XQHU 6 LOWHU 6RXQG 0L HU 6RXQG LOWHU 0RQR Q RPSRVLWH 9LGHR 9LVLRQ HPRGXODWRU 6FDUW QSXWV 6FDUW RXGVSHDNHU 063 2XWSXWV 063 XGLR 0RQLWRU 2XW The MSP3410 being able to process a wide range of TV standards shown below 79 6 VWHP 3RVLWLRQ RI 6RXQG FDUULHU 0 6RXQG 0RGXODWLRQ RORXU 6 VWHP RXQWU 0 6WHUH...

Page 59: ... carrier mute function The features of the MSP3410 IC2101 section are 9 Flexible selection of audio sources to be processed 10 Two Digital inputs and one output via I2S Bus for external Digital Signal Processing DSP processing for features such as Surround Sound and Astra Digital Radio ADR 11 Digital Interface to process ADR together with DRP3510A NOT USED 12 Performance of all de emphasis systems...

Page 60: ...the same time via the I2C bus the MSP IC2101 input ANA_IN2 pin 49 is selected by the internal switch and the D K S I F signal is input These signals at this stage have not been demodulated If A M sound is being received this signal is firstly demodulated in the I F stage before being passed to the MSP3410 IC2101 The A M demodulated sound is then fed to the MSP IC2101 via pin 44 NICAM which is a hi...

Page 61: ...being sound carrier 1 of the FM stereo system 20 2 2 Clock Generator To aid processing an external crystal is connected to pins 51 52 of the MSP3410 IC2101 this provides the required audio clock frequency for audio processing For Nicam F M Mono processing the MSP3410 IC2101 requires a clock frequency of 18 432MHz which it uses to lock to the sampling rate of the NICAM signal When processing FM ste...

Page 62: ...med by digital signal processing The DFP functions being grouped into three processing parts 1 Input Pre processing 2 Channel Selection 3 Channel Post processing The input pre processing is intended to prepare the various signals of all input sources in order to form a standardised signal at the input to the channel selector The signals are adjusted in volume by the prescaler before being processe...

Page 63: ... x 16bits per sampling cycle 32kHz to be transmitted 3 I2S_CL Synchronises the transmission of I2S serial data 1 024MHz 4 I2S_WS The I2S_WS word strobe line defines the data being transmitted either the left and right sample The I2S Bus has two possible modes of operation which are described and shown in the timing diagram below However only the standard mode of operation is used The standard mode...

Page 64: ... then fed to an internal analogue scart switching circuit which is used to select between the three scart signals input via pins 37 42 The selected audio signals are then fed via two A D converters before being input to the DFP processing stage Once the audio signals are fed to the DFP stage the signals are fed via a prescaler circuit which as mentioned previously adjust the volume of the audio si...

Page 65: ...o 20dB is carried out via the OSD The two filters coefficients for the selected range are set to the required value via the I2C bus 1 The volume modifications which occur during bass and treble adjustments are stabilised by limiting the internal volume to prevent clipping this limitation is carried out via software 20 4 3 Loudness The audio signal fed to the loudness stage is examined for loudness...

Page 66: ...en buffered and output via pins 24 and 25 of the MSP3410 IC2101 The signals output from the MSP3410 IC2101 are then fed via transistors Q2102 and Q2103 from here the signals are then fed to the input of IC251 audio output IC 20 4 5 Stereo Headphone Output path Headphone output signals are taken from the loudspeaker signal out which is routed via the headphone terminal This means that when the head...

Page 67: ...urround channels are used The Pro Logic decoders however which are referred to as active decoders uses a centre channel as well as the front left right and surround channels This means that the Dolby Pro Logic decoder generates clearer positioning of sounds and provides a full effect over a wider area of listening room This together with built in electronically assisted set up makes Pro Logic easi...

Page 68: ...ght and two surround speakers the surround channel being a mono signal The first of these five speakers the centre speaker is used to ensure clearer positioning of sounds In addition to this centre speaker there is also provision for external front left and right speakers via the phono output to an external amplifier however where this option is not used the internal left and right speakers of the...

Page 69: ...e left and right signals they remain completely independent Not so obvious is that there is also no theoretical loss of separation between the centre and surround signals Since the surround signal is recovered by taking the difference between the Lt and Rt the identical centre channel component in Lt and Rt will be exactly cancelled in the surround output Likewise since the centre channel is deriv...

Page 70: ...ams of the passive and active decoders below is input balance control this allows the user to change the program balance to correct for channel balance errors that may exist in the incoming audio signal this is vital to ensuring that the matrix stage gives optimum decoder performance Next the input signal is fed via a level control stage here the level is matched to the requirements of the decoder...

Page 71: ...their ratio Electrically this is no simple task but by taking the logarithm of each signal and subtracting one from the other it is possible obtain a measure of relative dominance Knowing which signal is dominant also includes knowing the encoded position or angle of the signal It is in this direction that enhancement must take place and may encompass any point in a 360E circle not just one of the...

Page 72: ...410 MSP3400 IC s as is here on EURO4 The DPL3519A IC2401 is also pin compatible to the MSP IC2101 The software control for the DPL3519A IC2401 is almost the same as for the MSP3400 IC2101 with the volume and tone controls using the same registers and values The main difference with the controlling software for the DPL3519A IC2401 is the addition of the Dolby Pro Logic control software that is requ...

Page 73: ...ding to table created by Dolby Laboratories 1ms steps 2 I2S input channels not used 2 I2S output channels not used Identical treble bass loudness function for L C R S 5 band equalizer for C channel Separate volume control for two surround outputs Mode control normal phantom wide three channel centre off panorama sound 3D Active stereo by pass Surround matrix mode control adaptive passive effect Ad...

Page 74: ...sing IC DPL3520 IC2401 Once the audio signals are fed to the DSP stage the signals are fed via a prescaler which adjusts the volume of the audio signal thus ensuring the signals are at the same level At the output of the prescaler the left and right audio signals split into two paths The first path feds the audio signals directly to the channel source selector which is the path used when the stand...

Page 75: ...eproducing a Dolby Pro Logic Active or Passive signal as well as providing a number of sound effects which are normally used when processing a mono signal When Dolby Pro Logic Active mode Normal Mode is selected the left L centre C right R and surround S signals are output from the Surround Decoder in signal pairs L and R C and S to the Channel Source Select switch Here the L R and C S signals are...

Page 76: ...rom this stage are then fed via their appropriate output channel path which are described next 24 4 3 Channel Output Path KHQ RQH RI WKH IROORZLQJ VLJQDO VRXUFHV KDV EHHQ VHOHFWHG E WKH XVHU WKH VHOHFWHG DXGLR VLJQDO LV RXWSXW YLD RQH RI WKH IROORZLQJ FKDQQHO RXWSXW SDWKV Stereo Mode When a standard stereo signal is selected the left and right audio signals are output from the channel source selec...

Page 77: ...ntrol with the adjustment settings being displayed on screen The balance control being switched OFF when processing more than 2 channels 24 4 5 Noise Sequencer As mentioned earlier a noise generator is also contained in the DPL3519A IC2401 which in normal operating conditions is switched OFF The noise generator is used to set the individual speaker levels of the L R C S channels To do this pink no...

Page 78: ...an external amplifier HQWUH XGLR 2XWSXW To be able reproduce the centre channel as well as the processing already described an additional board the C Board is used For those models without the C Board an external amplifier is required This centre signal which is output from pin 25 of IC2401 is fed via a buffer transistor Q2401 R2405 Here at R2406 the centre signal is split into the following paths...

Page 79: ...fer transistor Q2426 where the signal is fed via a low pass filter made up of R2508 C2467 Here only the low frequencies used for bass reproduction are fed via Q2428 which again has a muting transistor Q2427 in its base The Super 3D Bass signal is then fed via connector K5 pin 5 to the C Board via connector C2 after which the signal is then fed to IC2702 24 6 K Board Supply Voltage To carry out the...

Page 80: ...fied voltage is stabilised by a parallel switch mode power supply comprising of IC2701 and T2701 IC2701 containing a switching and stabilising circuit The power supply starting current is fed via resistors R2702 and R2703 to IC2701 pin 2 which causes Q3 IC2701 to turn ON causing a rising current to flow through P2 P1 via pin 3 pin 4 and R2709 The current flowing through winding P2 P1 will continue...

Page 81: ...urrent through the primary winding P2 P1 Likewise if the load on the secondary side increases the primary current reduces the feedback voltage decreases reducing the bias on Q1 which in turn increases the base bias of Q3 increasing the current flow 25 1 2 Over Current Protection If an increase in current occurs the excessive current flow through the primary winding P2 P1 causes a high current flow...

Page 82: ...ply gives TDA2030 a supply voltage of 36V However as this supply voltage is too large for the amplifiers TDA2030 when under load the supply voltage has to be reduced this is achieved by reducing the 18V supply rail thus reducing the overall supply voltage of TDA2030 As the load on TDA2030 increases the voltage drop across R2715 increases causing the base of Q2701 to become more negative with respe...

Page 83: ...and Super 3D Bass before being fed to the C Board Q2429 also controls the switch ON mute of the headphone amplifier and transistors Q2430 Q2431 Q2416 is also fed the switch ON mute signal which is then used to mute the L R C and S signals being fed to the phono outputs this muting being carried out by Q2417 Q2418 Q2419 Q2420 and Q2421 During switch OFF operations to control the muting transistors ...

Page 84: ...Order No TG 990802 Supplement Technical Guide Colour Television EURO 4 EURO 4H and EURO 4D Chassis Circuit Explanations 3DQDVRQLF XURSHDQ 7HOHYLVLRQ LYLVLRQ 0DWVXVKLWD OHFWULF 8 WG ...

Page 85: ... Chapter 3 Euro 4H Supplement 1 Control and Teletext Processing 19 2 F Board Processing 22 3 Colour Output Stage 36 4 AV2 Video Out Switching 39 5 Vertical Output 40 Chapter 4 Euro 4D Supplement 1 Power Supply 42 2 Digtal Video Broadcasting Power Supply 49 3 Microprocessor and Teletext Processing 57 4 Memory IC EAROM 66 5 Video Display Processor VDP 67 6 Dynamic Auto Focus DAF 68 7 Audio Signal Pr...

Page 86: ...with integrated Digital Video Broadcasting DVB terrestial decoder This supplemental technical guide should be used in conjunction with the EURO 4 Technical Guide and the relevant Service Manuals Only those differences which have arisen with the introduction of new models are covered in this Supplemental Technical Guide all other information is as presented in the EURO 4 Technical Guide TZS8EL001 A...

Page 87: ...the current fed toIC1901 IC1900Euro 4D pins 3 and 6 Pin 3 is fed to the inverting input of internal op amp1 while the input via pin6 isfed tothe non invertinginput of op amp2 The result of increasing this d c current to the invertinginput of op amp1isto reduceits output while the output of op amp2 is amplified increasing its output This results in the picture rotating in an anti clockwise directio...

Page 88: ...as shown in the diagram below The left and right audio signals output from pins 24 and 25 of IC2101 are now fed via the Acoustic Feedback AFB stage discussed in chapter 1 section 3 These changes are highlighted below The right audio signal output from pin 24 and the left output from pin 25 of the MSP3410 IC2101 are fed via transistors Q2102 and Q2103 to connector E10 pins 1 and 2 The right and lef...

Page 89: ...ese variations appear as peaks and troughs caused by factors such as cabinet speaker cone construction and ambient conditions To overcome these variations in frequency response a microphone is positioned within the speaker enclosure and is used to monitor the acoustic conditions This signal information being fed back to the AFB circuit Z Board where frequency shaping occurs thus providing a flat f...

Page 90: ...re being fed via a bass boost circuit in the form of an RC network made up of the following components capacitors C2227 C2228 and resistors R2233 R2230 R2231 and R2232 From this RC network the left audio speaker signal is input via pin 10 of IC2221 Here the feedback microphone signal input at pin 9 and the left speaker audio signal input at pin 10 are combined This results in a flat frequency resp...

Page 91: ...e user selected audio signal The microphone ON OFF control is fed from the headphone terminal located on the M Board and fed to the Z Board via connectors M7 and Z3 pin 1 Once on the Z Board the control line is fed to the base of two muting transistors Q2201 and Q2202 Transistor Q2201 being used to mute the right microphone audio signal and Q2202 muting the left Where the headphone terminal is not...

Page 92: ... they are amplified and output via pins 7 and 11 From here they are fed via the headphone terminal to connectors E6 and E7 to the internal speakers The usual negative feedback occurs from pin 11 to pin 1 and from pin 7 to pin 6 of the I C via the R C network R252 C254 and R258 and C259 The diodes at pins 2 and5D254andD253provide protectionfor theoutput I C against any voltage spikes by clamping th...

Page 93: ...3DQDVRQLF 10 ...

Page 94: ...et IC IC1105 which monitors the 5V supply line via pin 2 When the 5V supply falls to approximately 4 8V the reset IC IC1105 inputs a reset pulse via pin 54 of the microprocessor IC1101 Pin 71 VProt This input is used to detect a fault in the deflection circuit This is achieved by using the vertical synchronisation signal which is fed to the microprocessor IC1101 pin 47 via transistor Q1108 This si...

Page 95: ...al processing This is achieved by the reset control line output from pin 53 of the microprocessor IC1101 During switch ON the digital ICs are held LOW by Q1101 which is conducting at this point due to the 5V standby supply fed to the base of Q1101 via R1112 Once the supply voltages have become established pin 53 of the microprocessor IC1101 pulls the base of Q1101 LOW resulting in it switching OFF...

Page 96: ...m the vertical output IC IC451 pin 2 LA7845 or pin 3 LA7876 and fed to connector E4 to the P Board via connector P4 Once on the P Board the signal splits into two paths The first path feeds the vertical pulse to the vertical deflection coil which is fed via connector P3 The second path feeds the vertical signal via the zener diode D3921 and transistor Q3917 where the signal is amplified and fed to...

Page 97: ...3DQDVRQLF 14 Chapter 2 EURO 4 Supplement P Board DAF Circuit ...

Page 98: ...o fed to transistors Q3911 and Q3912 which provides a soft start at switch by grounding the horizontal drive signal applied to the gate terminal of Q3905 At switch on Q3911 is biased into conduction by the rising 12V supply line which is fed via R3974 to the base of Q3911 With Q3911 biased on the horizontal drive signal is grounded via the collector emitter junction Q3911 remains biased on until t...

Page 99: ...tical parabola waveform This combined signal is then output via the HV terminal to the D A F input terminal of the FBT T551 located on the E Board Here the signal is added to the focus voltage of T551 the focus voltage VF2with theD A F waveformsignal which is then supplied to the focus terminal on the CRT By this method the focus voltage for the central and outer edges of the scan undergo alterati...

Page 100: ...the relay contact of RL580 is opened This is achieved again under the control of transistor Q580 and pin 45 of the microprocessor IC1101 which pulls the base of Q580 LOW This results in the transistor switching OFF and the relay contact opening When thecontact of relay RL580is open the path the horizontal signal follows changes This sees the horizontal signal being fed from the horizontal scan coi...

Page 101: ...3DQDVRQLF 18 ...

Page 102: ...red AV interface The AV inputs being 1 AV1 21 pin scart socket allows composite video and RGB signal input Slow switching being provide via pin 8 for composite video input 2 AV2 21 pin scart socket also allows composite video input providing slow switching control via pin 8 AV2 also allows the input of an S VHS signal as does AV3 wide screen models only The internal TV signal selection is performe...

Page 103: ...g carried out via software control The results of this being used to back off the RGB output amplifiers in this I C to a greater or lesser extent thereby limiting the beam current Wherethecontrollimit is exceeded and theamplifiers have been completely reversed which may lead to an error in the RGB final outputs or there voltage supply defects in the CRT may result if no protective measures are tak...

Page 104: ...icroprocessor with data line SDA1 being output via pin 49 and SDA2 output via pin 51 while the required clock lines SCL1 and SCL2 are output from pins 48 and 50 consecutively While the operation of the I2C bus has not changed the ICs controlled by the I2C bus have these being The following are connected to I2C bus 1 On the F Board the VPC IC1501 CIP IC1502 SDA9401 IC1503 DDP IC1504 are responsble ...

Page 105: ...1 VPC3215 This device converts analogue luminance and chrominance signals to digital luminance and chrominance before the signals are processed by the internal comb filter and colour decoder Component Interface Processor IC1502 CIP3250 This CIP IC is used to convert the analogue RGB and fast blanking signals to digital and to perform signal selection SDA9401 IC1503 The SDA9401 on the F Board provi...

Page 106: ...the composite video signal which is fed from the tuner stage Pin 63 Cin allows the input of a chrominance signal which is input via the scart terminal of AV2 pin 15 or the 4 pin terminal of AV3 when an S VHS signal is input Thesevideo luminance andchrominance signalsare then fed to the internal analogue frontend which is the first processing stage of the VPC In this first processing stage the sign...

Page 107: ...ronous clock thus allowing unified architecture for all colour standards The colour decoder also provides some special modes such as wide band chrominance format which is intended for S VHS wide bandwidth chrominance If the adaptive comb filter of the VPC3215C IC1501 is used for luminance chrominance separation the colour decoder uses the S VHS processing mode The output of the colour decoder is Y...

Page 108: ...PC3215 IC1501 supports this feature using a letterbox detector The detector is used to detect black video lines by measuring the signal amplitude during active video For every field the number of black lines are measured compared to the previous measurement and the result is stored in the I2C register BLKLIN To adjust the picture amplitude the external controller reads this register calculates the...

Page 109: ...sing Synchronisation is provided by the Sync Processing stage the sync information extracted from the video luma signal being distributed internally to the rest of the video processing system Most of the processing that runs at the horizontal frequency is programmed by an internal Fast Processor FP 2 3 6 Control In addition to those signals mentioned above the VPC also provides the following clock...

Page 110: ...rted to 4 4 4 signal format before being fed to a mixer stage The digitised luminance and chrominance signals fed from IC1501 are input to IC1502 via pins 44 51 luma and 36 43 chroma The first stage these signals are fed is the format conversion stage used to convert the input signal format of 4 2 2 to 4 4 4 format for internal processing From this stage this signal is also fed to the mixer stage ...

Page 111: ...ial data input which is part of the I2C bus 1 control line CLK pin 54 This input provides a 13 5MHz clock which provides synchronisation and timing of the chrominance and luminance signals in IC1502 RSTN pin 55 The reset input which is an active LOW input is used to ensure correct operation after a power on This is acheived by keeping the CIP IC in a stable condition during this period ADC Clock B...

Page 112: ...ing Digital colour transient improvement Digital luminance peaking Motion adaptive temporal and spatial noise reduction Still picture 100 120 Hz interlaced scan 16 9 compatible Input Sync Controller Input Format Conversion Memory Controller ED Data Buffer Interfaces LDR Vertical Horizontal Decimation Noise Reduction and Measurement Motion Detector Movie Mode and Phase Detection LM Line Memory Scan...

Page 113: ...eing input via pin 54 is then used to read data out of the memory at the increased rate thus performing up conversion In addition to this up conversion the internal memory and HDR stage also allow the display of a still picture These now up converted luminance and chrominance signals are then output from IC1503 with the luminance signal being output from pins 1 3 7 63 and 64 while the chrominance ...

Page 114: ...st blank inputs Picture frame generator Deflection Scan velocity modulation output High performance H V deflection Separate ADC for tube measurements EHT compensation Miscellaneous I2C Bus Interface Single 5V power supply Contrast Interpolator Horizontal Scaler Measurement ADC Analogue I C 2 Clock FB In RGB Out SVM Sense 2H 2V 27MHz YC DDP3310 Digital RGB Matrix 3 x DAC 10 bit Tube Control Picture...

Page 115: ... Colour Transient Improvement DCTI The DCTI stage is used to sharpen the chrominance rise time which is achieved by applying a correction signal that is calculated by differentiating the colour difference signals The amount of correction is limited automatically The CrCb signals are then input to the matrix circuit where the luminance signal is added to the CrCb signals to produce a digital RGB si...

Page 116: ...circuit where the signal is independently adjusted for brightness and contrast The RGB signal is then inserted into the main RGB signal path under the control of the fast blanking pulse The control of white drive brightness and contrast adjustments being carried out on the RGB signals usingthe internalFast processor FP In the final stages before the selected analogue RGB signal is output cutoff an...

Page 117: ...ched to ensure that its input range is not exceeded The input range of the A D converter is dependant upon the measurement being taken and is controlled by pins 15 and 16 of the DDP IC1504 During cut off measurement the input range of the measuring A D converter is set by resistor R603 located on the E Board However as the white drive measurement contains alarger current range resistor R1538 is al...

Page 118: ...n safety input pin 11 This vertical protection input is used to prevent the picture tube from damage in the event of a malfunction of the vertical deflection stage If the peak to peak sawtooth signal is to small the RGB output signals are blanked 2 9 5 Control In addition to these signals mentioned above the DDP also requires the following Reset In pin 39 is used during the switch ON period to hol...

Page 119: ... Transistors Q908 and Q909 then output the signal at approximately 35Vpp to the SVM coil connected between connector Y5 pins 1 and 3 which is controlled directly via the collector terminals of transistors Q908 Q909 via resistor R929 which is coupled in parallel to the deflection winding 3 2 CRT AMPLIFIER STAGE 3 2 1 Outline In order to avoid damage caused by long cathode lines and there by trim th...

Page 120: ...nal pin 17 of the DDP IC1504 where this information is used to provide software controlled beam current regulation 3 4 BEAM CURRENT LIMITATION The measurement of the beam current as mentioned in the previous section is fed via the Sense input of the DDP IC1504 pin 17 the result of the measurement being compared to the value stored in memory The result of which is used to reduce the drive of the br...

Page 121: ...3DQDVRQLF 38 Chapter 3 EURO 4H Supplement Y Board Schematic ...

Page 122: ...g of the luminance and chrominance signals to produce a video signal which is described in the EURO 4 Technical Guide section 18 of the M Processing Stage This newly combined video signal is then fed to the E Board via connector E15 and is fed to pin 8 of IC601 The video signal is then output from pin 6 and fed to the video output pin 19 of AV2 Likewise video out fed from the VPC pin 64 to the E B...

Page 123: ...This brief additional energy requirement is met by increasing the supply voltage available to the output stage by 3 times the supply During vertical sweep the bootstrap capacitors C456 and C463 are charged up to almost supply voltage via D454 and D458 The output of the pump up generators at pins 8 9 and 10 of IC451 are at this moment ground potential As a result of the DC displacement at the negat...

Page 124: ...3DQDVRQLF 41 ...

Page 125: ...Board via the main TV ON OFF switch S802 to connector M11 The A C voltage is then fed from the M Board and connector M11 to the W Board and connector W1 where the A C supply is fed to the standby transformer T802 At thestandby transformerT802 theA C supplysplits into three paths The first path sees the A C supply being fed to the normally open contact of the standby relay RL801 The second path has...

Page 126: ...upply being used to reduce the load on the standby transformer when the TV is in normal operation The second path the supply takes is via resistor R862 to the base of transistor Q852 This supply being regulated by the zener diode D873 which is used as a base bias 3 The second path from the standby transformer T802 that the supply voltage follows is via the rectifying diode D867 and smoothing capac...

Page 127: ...ows thesupply tofulfil bothpower on and standby roles The IC features pulse by pulse overcurrent protection over voltage protection with latch and thermal protection functions 1 2 1 General The mains A C voltage which flows via the standby relay isthenfedvia connectorW2 tothe connectorE1 located on the E Board as mentioned earlier Once the A C supply isinput ontothe E Board the supplyis fed via th...

Page 128: ... approximately 16V IC801 begins to operate and drive the internal MOS FET transistor into conduction resulting in current flow via the primary winding of T801 pin 3 drain terminal and pin 2 source terminal of IC801 Once IC801 begins to operate the supply voltage at pin 4 is supplied via the rectifying diode D803 and smoothing capacitor C816 which is fed from the drive winding of the switching tran...

Page 129: ...ding P2 P1 stops This results in the collapse of the magnetic field of T801 and the energy stored in the primary winding is transferred to the secondary windings During this period the voltage at pin 1 of IC801 begins to fall at a rate determined by C819 When the internal comparator of IC801 detects that the voltage at pin 1 is below the internally generated 0 73V reference signal the MOS FET is s...

Page 130: ...pin 4 begins to rise again but when it reaches the start up level 16V the latch circuit continues to stop the drive When the latch is ON Vcc pin 4 voltage increasesand decreases within the 10V to 16V range as shown in figure 1 and is prevented from rising normally Cancellation of the latchis achievedby switchingOFF the TV and disconnecting the AC input to the circuit 1 6 5 150V Line Protection In ...

Page 131: ...oltages for the line output stage 29V supply for the A F output stage 1 7 1 Voltage Stabilisation The stabilisation of the previously mentioned secondary supplies is performed as follows A 15V supply which is fed from the transformer T801 is fed to pin 1 of IC851 which is used to produce a stabilized 12V supply This 12V supply is also fed to IC853 pin 1 which produces a stabilised 8V supply output...

Page 132: ...ed on the W Board is used ThesupplyvoltagesfortheDVBdecoder areprovided by the integrated circuit STR F6653 IC4801 The A C mains supply voltage input via connector M10 of the M Board is fed via the main TV ON OFF switch S802 to connector M11 The A C voltage is then fed from the M Board and connector M11 to the W Board and connector W1 where the A C supply is fed to the standby supply circuit discu...

Page 133: ...or Q4851 is biased into conduction resulting in current flow taking place via the DVB relay RL4801 and the collector emitter junction of transistor Q4851 this current flow causing the normally open relay contact to close When the relay contact closes the mains A C supply is fed to the bridge rectifier D4802 Here the A C supply is fully rectified before being smoothed by capacitor C4809 Thissupplyv...

Page 134: ...ce IC4801 begins to operate the supply voltage at pin 4 is supplied via the rectifying diode D4808 and smoothingcapacitorC4810whichisfedfrom thedrive winding of the switching transformer T4801 This supply voltagewhich isfed fromthe drivewinding V1 of T4801 is initially unable to provide the supply voltage demanded and so the voltage at pin 4 decreases The charge held by C4810 however slows this de...

Page 135: ...rred to the secondary windings During this period the voltage at pin 1 of IC4801 begins to fall at a rate determined by C4806 When the internal comparator of IC4801 detects that the voltage at pin 1 is below the internally generated 0 73V reference signal the FET transistor is once again switched ON and the cycle is repeated 2 4 Regulation The power supply ON time is controlled by controlling the ...

Page 136: ...detected by inputting the voltage drop developed across R4805 R4807 into pin 1 of IC4801 via the noise filter circuit R4806 C4807 When this input voltage exceeds the internally generated reference signal 0 73V the drive output is pulled LOW resulting in the internal FET transistor of IC4801 switching OFF and the power supply stopping 2 5 4 Latch The latch circuit is used to keep the output from th...

Page 137: ... to supply operating voltages to the DVB digital processing ICs 2 5V supply used by the conditional access module 3 32V to supply the digital tuner Although the secondary voltages are relatively stable with short term load variations being compensated for by IC4801 it is still necessary to stabilise the following voltages both 5V supplies 9V and 12V 9 7R SLQ URP 9 7 ...

Page 138: ... monitored by IC4853 via the regulator R terminal The regulator input being connected to the 5V supply via a voltage divider consisting of resistors R4871 R4872 If any load variations are detected by IC4853 the cathode K terminal output will increase or decrease the base bias of transistor Q4856 The base bias being fed from the 12V line via R4866 By adjusting this base bias of Q4856 by a greater o...

Page 139: ...ction Now with transistor Q4854 conducting the base of transistor Q4855 is pulled LOW this resulting in Q4855 also conducting With transistor Q4855 conducting pin 2 of IC4852 is then pulled LOW switching OFF IC4852 Cancellation of the latch circuit operation is achieved by switching OFF the TV disconnecting the A C input to the power supply circuit 2 8 3 12V Protection Likewise the 12V supply line...

Page 140: ...processor IC1101 on the EURO 4D chassis is the same as EURO 4 some pindifferences do occur these differences being highlighted in the following sections The First area looked at being control processing stage of the microprocessor DSWXUH DWFKGRJ 7LPHU RPSDUH 7LPHU 3 0 77 936 6OLFHU FTXLVLWLRQ LVSOD KDUDFWHU LVSOD HQHUDWRU 38 WHQGHG DWD 5 0 WH 0HPRU XDO3RUW QWHUIDFH XIIHU LVSOD 5 0 7LPLQJ XDO3RUW Q...

Page 141: ... At switch ON this supply is less than 4 8V which results in the reset IC IC1104 pulling the reset line LOW this LOW level thus causes the diode D1112 to conduct resulting in transistor Q1118 being biased into conduction feeding a HIGH level to pin 8 of the microprocessor IC1101 The ALE controlline pin8 isheld HIGHuntil thesupply voltages have become established at which time pin 1 of IC1104 goes ...

Page 142: ...e format of 4 3 supply aslow switchcontrol voltageof 12V and those with an aspect ratio of 16 9 supply a slow switch control voltage of 6V These switching voltages which are fed to the microprocessor pins 58 AV1 and 59 AV2 as mentioned previously are fed via the potential divider resistors R1131 R1128 and final R1127 to pin 59 for AV2 selection AV1 selection is fed via resistors R1130 R1129 and R1...

Page 143: ... During normal operation the beam current is measured with the result being input via the sense input of VDP IC601 pin 28 The beam current limitation is carried out via software control with the results of this being used to back off the RGB output amplifiers in this I C to a greater or lesser extent thereby limiting the beam current Where the control limit is exceeded although the amplifiershaveb...

Page 144: ...ssor IC1101 are used to display the required teletext and OSD information on screen The RGB signals being output from the following terminals Blue pin 39 Green pin 38 Red pin 37 Pin 40 Blanking The blanking pulse output from the microprocessor IC1101 pin 40 is used to provide the required switching control for the teletext and OSD displays Pin 52 ON OFF This output is responsible for switching the...

Page 145: ...Control of the DVB LED is via pin 69 of the microprocessor IC1101 which when in operation feeds a LOW level to Q1013 on the M Board This LOW level results in Q1013 switching ON and the DVB LED is illuminated Pin 73 In This control line output from pin 73 of the microprocessor IC1101 is used as an interrupt control line between the UART IC IC1107 located on the T Board the microprocessor IC1101 on ...

Page 146: ...h TV and video are Project 50 compliant 1 Tuner preset data down load TV VCR 2 What You See Is What You Record Direct TV In addition to thesefeatures theTV Video alsoinclude in their protocol Automatic signal matching signal quality Here the TV video at first time of connecting send information regarding each others features and operation capabilities such as the signal standards they can processe...

Page 147: ...ception of both the Teletext TTX and Video Programme Signal VPS The VPS feature is not used Display Timing which is used to ensure that the text information is locked to the same timing as the raster scan Character ROM which provides the required characters for display of text information on screen Display Generator used to create the Text display DSWXUH DWFKGRJ 7LPHU RPSDUH 7LPHU 3 0 77 936 6OLFH...

Page 148: ... and the signal quality of the TV channel The text data is then fed via the dual port interface to the buffer where under the control of the internal CPU thedataisstoredinthedisplayRAMuntilthe TTXdata is required When the TTX data is requested the information is read out of the Display RAM via the interface and fed to the Display Generator The display generator then selects the pixel information f...

Page 149: ...ch contains the command for reading out The address word ischecked forcompatibility withthe address contained in the IC and acknowledged by an acknowledgement bit The memory location address is then transmitted by themaster I C in thiscase themicroprocessor This address also consists of an 8 bit word whose reception is again confirmed by an acknowledgement bit If this is the case the 8 data bits a...

Page 150: ...in 13 of IC3401 and fed to the VDP IC601 pin 60 Pin 61 Vin1 RFV This input which is fed from the video switching IC IC3401 pin 14 is fed either a video signal from the tuner or the luminance signal from the DVB decoder Pin 62 Vin2 AV1V This input is still fed the video signal fed from the 21 pin scart terminal AV1 pin 20 directly to pin 62 Pin 63 Vin3 AV2V This input is still fed the video signal ...

Page 151: ...in 2 LA7845 where the signal then splits into two paths The first path feeds the vertical pulse to the vertical deflection coil which is fed via connector E4 The second path feeds the vertical signal via the zener diode D3931 and transistor Q3921 where the signal is amplified and fed to connector E66 pin 5 here the vertical signal is passed to the W Board via connector W6 Once on the W Board the v...

Page 152: ...3DQDVRQLF 69 Chapter 4 EURO 4D Supplement P Board DAF Circuit 9 5 9 H U W L F D O 3 U R W H F W L R Q Q R U L R Q W D O Q 0 R G H O H S H Q G D Q W 0 R G H O H S H Q G D Q W ...

Page 153: ...nto the following vertical oscillator The vertical oscillator is set via pin 16 while the timing of the oscillator is set via pin 18 From the oscillator stage the vertical pulse is fed to the vertical drive stage the amplitude of the vertical pulse being set by R3927 R3918 connected to pin 19 The vertical pulse is then output via pin 21 synchronisedbythe verticalflyback pulseinput viapin 22 This v...

Page 154: ... 4 3 mode Where a normal composite or S VHS signal is processed and displayed on screen horizontal compression and expansion takes place in the horizontal scaler stage within the VDP However the RGB signal which is also fed to and processed by the VDP is inserted after the VDP s horizontal scaler stage meaning that no horizontal compression can take place To over come this problem located on the E...

Page 155: ... changes This sees the horizontal signal being fed from the horizontal scan coil as mentioned earlier via capacitor C596 the relay contact and coil L595 The relay contact short circuiting L590 R590 and C590 The horizontal signalisagainfinallyfedviacoilsL595 L591 andL594 back to the FBT During these periods of 4 3 display the 147V supply voltage to the DAF circuit is also reduced This is achieved b...

Page 156: ... RXW 7 1 Input Signal Processing Path Pin 47 ANA_In1 This signal input has not changed the signal input via pin 47 of the MSP IC2101 being fed directly from the tuner SIF output Pin 37 Pin 38 SC3_In_L _R Again this input processing path has not changed the left and right audio signals fed from AV3 RCA terminals being fed directly to the MSP Pin 39 Pin 40 SC2_In_L R Thisinput processing pathagain h...

Page 157: ...lt in the right audio signal being output from pin 24 and the left audio signal being output from pin 25 of the MSP3410 IC2101 From here the left and right audio signals are then fed via transistors Q2102 and Q2103 The right and left audio signals are then fed to the Z Boardwherethe audiosignals areprocessed bythe Acoustic Feedback AFB stage discussed in chapter 1 section 3 Pin 27 SC2_Out_R The ri...

Page 158: ...located on the E Board its operation being discussed in section 10 1 of the EURO 4 Technical Guide During the ON and OFF periods the mute control signal is fed via connectors E22 M6 pin 4 to the emitter of transistor Q2435 The mute control line during the ON OFF periods is of a HIGH level which causes transistor Q2435 into conduction biasing on transistors Q2436 and Q2437 which mute the left and r...

Page 159: ...s the selection between the analogue TV signals and the DVB signals This selection can be found under the Setup Menu labelled as AV2 out where the options for Analogue DVB and Monitor can be made These three options being discussed below 1 Analogue This option allows the standard analogue TV signals be output via AV2 Once an analogue TV signal has been selected you are then free to change to a DVB...

Page 160: ...minance signals is provided by IC3401 TEA6415C This IC consists of a switching matrix which has eight inputs five fixed level outputs and one variable gain output The switching of this matrix is controlled via I2C bus 4 at pins 2 and 4 This makes it possible to have multipleinputs andoutputs switchedat thesame time ...

Page 161: ...nterference occurs in any of the subsequent processing paths To detect a chrominance signal output via pin 15 ad c bias level is applied to the chrominance signals input to the switching IC IC3401 this isachieved via100K resistors located at the inputs This d c bias is then used to switch transistor Q3441 ON allowing the chrominance signal to be buffered and output via Q3441 where the signal is sp...

Page 162: ...o Switching Outline The audio switching is performed by IC3151 TEA6420 This switching matrix has the same features as the TEA6415 except that it contains a left and right matrix with five inputs and four outputs I2C bus 4 control is via pins 23 and 24 ...

Page 163: ...left audio signal see pin 19 Pin 20 Mon Rin Input at pin 20 is the right audio signal which is output from the MSP IC2101 pin 30 and which is output to both AV1 pin 1 of the 21 pin scart terminal and the monitor audio output terminal JK3403 located on the H Board Pin 21 TV Rin The input at pin 21 sees the right audio signal output fromthe MSPIC2101 pin27 locatedon theE Board this right audio signa...

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