Panasonic EURO 4 Chassis, Technical Manual

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3DQDVRQLF
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Chapter 4 EURO 4D Supplement
3.1.3. Q-Link
:
AV_Link
The AV_Link control line is used to transfer
information and user functions between the TV and
VCR via pin 10 of the 21 pin scart terminals using a
21
pin socket lead which conforms to the
EUROCONNECTOR standard.
The transfer of data fed from the TV to the VCR is
output from pin 72 of the microprocessor IC1101 via
the AV_Link_OUT control line, this data with its dc
level biases transistor Q1106. into conduction,
feeding the data to pin 10 of AV2 via the AV Link
control line.
Likewise data transferred from the VCR to the TV is
again fed via pin 10 of the 21 pin scart terminal (AV2).
Here data input from the VCR is fed via the AV Link
control line to transistor Q1107, which is configured to
function as a diode. When the data input to the TV
which has a dc level of approximately 5V is applied to
the collector of Q1107, transistor Q1107 conducts
feeding the input AV Link data via transistors Q1105,
Q1104. At the output of transistor Q1104 the AV Link
data is then fed to the T-Board and the UART IC where
this AV Link data is acted upon.
The type of data and function control information fed
via the AV_Link is as follows:
1. TV Auto Power ON: TV automatically turns ON
when the VCR starts play-back.
2. VCR Auto Standby: VCR will automatically
switch to standby when the TV is turned OFF,
unless the VCR is in recording mode.
3. TV On screen Display of VCR status.
4. Down load of Country selection.
These above features will only work with a Panasonic
TV / video combination who are both Q-Link (Project
50+) compliant.
The features below will work with different brands of
TV and video combinations, again as long as both TV
and video are Project 50 compliant.
1. Tuner preset data down load (TV->VCR)
2. What You See Is What You Record (Direct TV)
In addition to these features the TV/Video also include
in their protocol Automatic signal matching (signal
quality). Here the TV/video at first time of connecting
send information regarding each others features and
operation capabilities, such as the signal standards
they can processes and whether they are able to
process and display 16:9 format as an example.
3.1.4. I
2
C Bus
:
Pin48,49-SCL1,SDA1
Pin 50, 51-SCL2, SDA2
Pin 44, 45 - SCL4, SDA4
The I
2
C - bus systems are generated by the
microprocessor, with data line SDA1 being output via
pin 49, SDA2 output via pin 51 and SDA4 output via
pin 44, while the required clock lines SCL1, SCL2 and
SCL4 are output from pins 48, 50 and 44
consecutively.
The following are connected to I
2
C- bus 1:
The video and deflection processor (VDP) IC601, for
processing of the composite video signal and
deflection processing.
The multi standard sound processor (MSP) IC2101,
for processing of the sound signals.
The tuner and I.F. stage where signal selection and
processing is performed.
The 21 pin AV1 socket pins 10 and 12 is fed the
I
2
C-bus1 control line via the transistors Q3006 and
Q3007. During service mode, therefore, the T.V. may
be programmed with the aid of an external memory
pack.
PLEASE NOTE: Even though the above option is still
available when in Service Mode, the EAROM of the
EURO 4D Chassis is 32k bits and the Memory Pack
is only 16k bits. This means that the memory pack is
unable to store all the EAROM data.
The following are connected to I
2
C- bus 2 :
The EAROM IC1102 is the only IC connected to I
2
C-
bus 2, which contains system data, programme
locations and specific tuning values, normal levels
etc.
Connected to I
2
C- bus 4:
The Video switching IC IC3401 and the audio
switching IC IC3151, both ICs being located on the
H-Board.