Omron NYP - 1 Series, Hardware User Manual

Page: 234 / 266


BIOS - Chipset BIOS up to version 008
This section provides Chipset information for 7
th
generation CPUs:
• Intel
®
Core
™
i5-7300U with a BIOS version up to BU
£££
008
• Intel
®
Celeron
®
3965U with a BIOS version up to BV
£££
008
For all other CPU types or BIOS versions refer to BIOS - Chipset on page A-25 for details.
Changeable BIOS Chipset parameters and their factory default values:
Item Default / Remark
Processor
(Integrated
Components) Memory Configuration / Memory Thermal Configuration Refer to Memory
Thermal Configuration
on page A-31 for de-
tails.
Memory Configuration / Memory Training Algorithms
Early Command Training Disabled
SenseAmp Offset Training Enabled
Early ReadMPR Timing Centering
2D Enabled
Read MPR Training Enabled
Receive Enable Training Enabled
Jedec Write Leveling Enabled
Early Write Time Centering 2D Enabled
Early Write Drive Strength / Equal-
ization Enabled
Early Read Time Centering 2D Enabled
Write Timing Centering 1D Enabled
Write Voltage Centering 1D Enabled
Read Timing Centering 1D Enabled
Dimm ODT Training* Enabled
Max RTT_WR ODT Off
DIMM RON Training* Enabled
Write Drive Strength/Equalization
2D* Disabled
Write Slew Rate Training* Enabled
Read ODT Training* Enabled
Read Equalization Training* Enabled
Read Amplifier Training* Enabled
Write Timing Centering 2D Enabled
Read Timing Centering 2D Enabled
Command Voltage Centering Enabled
Appendices
A-26
NY-series Industrial Panel PC Hardware User's Manual (W555)