The
Duty Cycle (DUTY)
setting measures the percentage of time a pulse is active (high) over the total period
of the signal. The duty cycle measurement allows reading the input from PWM control signals.
The
Phase Delay (DELAY)
mode measures the delay time in msec between the rising edges of Pulse A and
Pulse B inputs. Note the Pulse B input replaces the functionality of the Enable input. This function is
intended to be used on two input pulses operating at the same frequency but with different phase offsets.
The
Up Counter/Totalizer (COUNT)
mode counts the number of rising edges while the Enable input is active
until the Reset input is activated. The Enable Input (Pin 4) acts as a Stop/Start for the Up Counter when
pulled up to 3.3 V. If the Enable Input is
Inactive
, it will pause/stop the up counter until it is re-enabled. If
the Enable Input is
Active
, it will start the up-count. Activating the Reset input (Pin 5) will reset the counter
back to 0. The Reset and Enable inputs can be configured to be active high or active low by configuring the
Enable Input to Pull-Down (PD). See the
Input Configuration Diagrams
section for details.
Duty Cycle = X / Y %
X
Y
Figure 12: Duty cycle example
PULSE
RESET
Counts the number of pulses
while Reset is inactive and
Enable is active
Figure 14: Up Counter/Totalizer example with Active High Reset and Enable
Counter resets to 0 when
reset is active
PULSE_B
Measure the time between rising
edges of PULSE_A and PULSE_B
Figure 13: Phase Delay example
ENABLE
Pauses the number of pulses
while Reset is inactive and
Enable is inctive
PULSE_A
1
3
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