Oki MSM9225B, User Manual

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MSM9225B User’s Manual
Chapter 2 Register Descriptions
2 – 34
2.4.10 CAN Control Register 2 (CANC2: 8Fhex)
This is a register to control bus off release and error counter operation.
The bit configuration is shown below.
At reset, this register is set to “0000 0000”.
MSB Not
used
Not
used
Not
used
RSTEC
Not
used
Not
used
Not
used
COMPAT
LSB CANC2 (8Fhex), R/W: R/W
Initial
value:
0 0 0 0 0 0 0 0
0
Just as in the MSM9225, a bus off
state will be released if 11
consecutive “recessive” bits are
received 128 times.
1
If the INIT bit of the CANC register
(0Ehex) is set to “0” from “1”, the bus
off release operation is started.
Unused bit.
Write a “0”.
0 Error counter value is not reset.
1 Error counter value is reset.
Unused bit.
Write a “0”.
Figure 2-33 CAN Control Register 2 (CANC2)
(1) Bus off release start timing: COMPAT
This bit specifies bus off release start operation.
When this bit is “0”, the bus off state will be released if 11 consecutive “recessive” bits have been
received 128 times since the time immediately after the bus off state was entered. This is the same
operation as the MSM9225.
When this bit is “1”, the bus off state will be released if 11 consecutive “recessive” bits have been
received 128 times since the point of time that the INIT bit of the CAN control register (CANC: 0Ehex)
was set to “1”, then set to “0”.
(2) Error counter reset: RSTEC
This bit specifies whether to reset the error counters (both transmit error counter and receive error
counter).
Setting this bit to “0” does not reset the error counters.
The error counters will be reset if the RSTEC bit is set to “1” when the COMPAT bit is “1” and the INIT
bit of CANC is “1”. Set the RSTEC bit to “0” after setting it to “1”.
When the MSM9225B is in the bus off state, this operation is invalid. (Even if the above operation is
done, the error counters are not cleared and the bus off state also is not released.)
B