Oki MSM9225B, User Manual

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MSM9225B User’s Manual
Chapter 2 Register Descriptions
2 – 21
2.4.3 Message Box Count Setting Register (NMES: 1Ehex)
This is a register to set the number of message boxes to be used.
A maximum of 16 message boxes can be set, with message box numbers 0 to F.
Writing to NMES is enabled when initialize bit INIT of the CAN control register (CANC: 0Ehex) is “1”.
At reset, NMES is set to “00000000”
The bit configuration and relationship between message box number and number of message boxes are as
follows:
MSB Not
used
Not
used
Not
used
Not
used
NMES3 NMES2 NMES1 NMES0
LSB NMES (1Ehex), *R/W: R/W
Initial
value:
0 0 0 0 0 0 0 0
NMES3 NMES2 NMES1 NMES0
Number of message boxes
0 0 0 0 1 (message box 0)
0 0 0 1 2 (message boxes 0, 1)
•
• •
• •
• •
• •
•
1 1 1 0 15 (message boxes 0–E)
1 1 1 1 16 (message boxes 0–F)
Unused bit.
Write a “0”.
Figure 2-21 Message Box Count Setting Register (NMES)
2.4.4 CAN Bus Timing Register 0 (BTR0: 1Fhex)
The MSM9225B has an internal baud rate prescaler that generates the BTL (Bit Timing Logic) signal by
dividing the system clock by a factor of 1 to 64. BTL is the system clock for the communication function.
The register BTR0 sets the baud rate prescaler and the SJW width.
Writing to BTR0 is enabled only when the initialization bit INIT of the CAN control register (CANC: 0Ehex)
has been set to “1”.
The bit configuration is shown below.
MSB SJWB SJWA BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 LSB BTR0 (1Fhex), *R/W: R/W
Initial
value:
0 0 0 0 0 0 0 0
BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 BTL Cycle time
0 0 0 0 0 0 1
×
system clock period
0 0 0 0 0 1 2
×
system clock period
•
• •
• •
• •
• •
• •
• •
•
1 1 1 1 1 0 63
×
system clock period
1 1 1 1 1 1 64
×
system clock period
System clock: the clock 1/2 the frequency of the oscillator clock.
SJWB SJWA SJW1, SJW2
0 0 1
×
BTL cycle
0 1 2
×
BTL cycle
1 0 3
×
BTL cycle
1 1 4
×
BTL cycle
Figure 2-22 CAN Bus Timing Register 0 (BTR0)