Oki MSM9225B, User Manual

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MSM9225B User’s Manual
Chapter 2 Register Descriptions
2 – 24
Table 2-8 TSEG2 Setting
TSEG22 TSEG21 TSEG20 TSEG2
0 0 0 1
×
BTL cycle
0 0 1 2
×
BTL cycle
•
•
• •
•
• •
•
• •
•
•
1 1 0 7
×
BTL cycle
1 1 1 8
×
BTL cycle
(3) Bit timing
Bit timing is set by CAN bus timing registers 0 and 1 (BTR0, 1). Figure 2-24 shows the relationship
between 1 bit time of a message and CAN bus timing.
1 bit time
SJW1
(BTR0 : SJWB/A)
TSEG1
(BTR1 : TSEG13-10)
TSEG2
(BTR1 : TSEG22-20)
SJW2
(= SJW1)
1BTL
cycle
Sampling
point
Transmit
point
PROP-SEG SYNC-SEG PHASE-SEG1 PHASE-SEG2
Figure 2-24 Bit Timing
Explanation of Terms Used
•
Sync segment: The segment in which the falling edge is detected and the bit synchronization is started.
•
Prop segment: The segment for compensating for the delay of the output buffer, the CAN bus, and the
input buffer. Set so as to wait until ACK is returned before the start of phase segment 1.
Period of prop segment time
≥
(output buffer delay + CAN bus delay + input buffer delay)
•
Phase segment 1, 2: These are the segments for compensating the error in the data bit time. Although a
larger tolerance can be established when these are large, the communication speed becomes slower.
•
SJW1, 2: These are the bits for setting the range of bit synchronization. SJW is the abbreviation for
reSynchronization Jump Width.
If setting is :
BTR0 = “01000001” SJWB = “0”, SJWA = “1”, BRP5-0 = “000001”
BTR1 = “00000001” TSEG2 = “000”, TSEG1 = “0001”
then the bit timing is as follows:
Sync segment 1 BTL cycle (fixed)
SJW 1 2 BTL cycle
TSEG 1 2 BTL cycle
TSEG 2 1 BTL cycle
SJW 2 2 BTL cycle
1 bit time 8 BTL cycle
Sampling point = 5 BTL cycle
If f
OSC
= 16 MHz, then 1 BTL cycle is :
BTL cycle = 2
×
(BRP setting value + 1)/f
OSC
= 2
×
(1 + 1) / 16 MHz = 0.25 µs
Therefore 1 bit time is :
8 BTL cycle = 8
×
0.25 µs = 2.0 µs
(= 500 kbps)