NXP Semiconductors QorIQ T1040, User Manual, Page: 49 / 68

3.2.8 Flash control and status register (FLHCSR)
Address: 0h base + 13h offset = 13h
Bit 0 1 2 3 4 5 6 7
Read BOOT_SEL
BANK_OR
SW_BANK_
SEL0
SW_BANK_
SEL1
SW_BANK_
SEL2
BANK_
SEL0
BANK_
SEL1
BANK_
SEL2
Write
Reset n 0 n n n 0 0 0
FLHCSR field descriptions
Field Description
0
BOOT_SEL
0: Boot from 16-bit NOR flash.
1: Boot from 8-bit NAND flash.
1
BANK_OR
0: NOR flash bank select from CPLD override disable.
1: NOR flash bank select from CPLD override enable.
2
SW_BANK_SEL0
NOR flash bank select bit0 of switch status is 0.
1: NOR flash bank select bit0 of switch status is 1.
3
SW_BANK_SEL1
0: NOR flash bank select bit1 of switch status is 0.
1: NOR flash bank select bit1 of switch status is 1.
4
SW_BANK_SEL2
0: NOR flash bank select bit2 of switch status is 0.
1: NOR flash bank select bit2 of switch status is 1.
5
BANK_SEL0
0: NOR flash bank select bit0 set 0.
1: NOR flash bank select bit0 set 1.
6
BANK_SEL1
0: NOR flash bank select bit1 set 0.
1: NOR flash bank select bit1 set 1
7
BANK_SEL2
0: NOR flash bank select bit2 set 0.
1: NOR flash bank select bit2 set 1.
3.2.9 Fan control and status register (FANCSR)
Address: 0h base + 14h offset = 14h
Bit 0 1 2 3 4 5 6 7
Read
Reserved FAN_PWM
Write
Reset
Chapter 3 CPLD specification
QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015
Freescale Semiconductor, Inc. 49