T1040
POR & Override
CPLD Register
CPLD
cfg_xxx
switch
Figure 2-21. CPLD and DIP switch connection
The table below shows how POR configuration is done through switches.
NOTE
0 and 1 are represented by ON and OFF respectively on the
board.
NOTE
The recommended value for the switch settings for NOR flash
is below. Refer this for value of reserved switches:
SW1: 0001 0011
SW2: 1011 1011
SW3: 1110 0001
Table 2-12. POR configuration through switches
Switch
Signal name
Pin Name
Signal meaning
Setting
SW1[1:8]
cfg_rcw_src[0:7]
IFC_AD[8:15]
Reset Configuration
word source
Detail description see
T1040 RM
SW2[1]
cfg_rcw_src[8]
IFC_CLE
Reset Configuration
word source
Detail description see
T1040 RM
SW2[2]
cfg_ifc_te
IFC_TE
IFC external transceiver
enable polarity select
0: IFC drives logic 1 for
TE assertion
1: IFC drives logic 0 for
TE assertion
SW2[3]
cfg_pll_config_sel_b
IFC_A18
Reserved
Reserved
SW2[4]
cfg_por_ainit
IFC_A19
Reserved
Reserved
Table continues on the next page...
Chapter 2 Architecture
QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015
Freescale Semiconductor, Inc.
39
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