HWVER field descriptions
Field
Description
0–7
HW_VER
The version field of the hardware board.
3.2.4 Software version register (SWVER)
Address: 0h base + 3h offset = 3h
Bit
0
1
2
3
4
5
6
7
Read
Write
Reset
* Notes:
SW_VER field: n=Depends on PLD image version
•
SWVER field descriptions
Field
Description
0–7
SW_VER
The version field of the CPLD software.
3.2.5 Reset control register (RSTCON1)
Address: 0h base + 10h offset = 10h
Bit
0
1
2
3
4
5
6
7
Read
Write
Reset
0
0
0
0
0
0
0
0
RSTCON1 field descriptions
Field
Description
0
SW_RST
0: No reset occurs.
1: Writing logic 1 will produce whole board reset# signal, this bit can auto clear.
1
-
This field is reserved.
2
EC1_RST
0: No reset occurs.
1: Write a logic 1 produces RGMII PHY1(RTL82111E-VB) reset# signal, this bit can auto clear.
3
EC2_RST
0: No reset occurs.
1: Writing logic 1 produces RGMII PHY2(RTL82111E-VB) reset# signal, this bit can auto clear.
Table continues on the next page...
CPLD memory map
QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015
46
Freescale Semiconductor, Inc.
Summary of Contents for QorIQ T1040
Page 1: ...QorIQ T1040 Reference Design Board User Guide Document Number T1040RDBPAUG Rev 0 06 2015...
Page 2: ...QorIQ T1040 Reference Design Board User Guide Rev 0 06 2015 2 Freescale Semiconductor Inc...
Page 6: ...QorIQ T1040 Reference Design Board User Guide Rev 0 06 2015 6 Freescale Semiconductor Inc...
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